Initializing issues with DE2 -DM9KA

[Altera_Forum]

Hello, I opened this thread because I am currently stuck at a problem that a still can't point what is the problem with my code working on the DE2 Altera board and Quartus 13.01v. 

I tried to encounter this problem from different angles for many hours but without any success yet. The problem is that when trying to write and then reading data to bus or from the bus INOUT, a still don’t get any response from the DM9ka controller after trying to reset some of the registers according to the program guide book of the device and other websites. I have been trying to check again if the signals and timing is ok but still don’t get any values only zeros at output (but have a response of INT from device). Tried also to read only the 28h and 29h registers for vendor device ID but still the same.  The project is based on a module DM9ka for receiving packets only from Ethernet MAC layer And then processing it in a pipeline method -this other module works ok for now (I don’t want to use Qsys).   Thx in advance.:)  Some pictures and the code sample of the project:

[Altera_Forum]

?! someone can please help me with that issues - 

I tried to change the signals and give more time delay such that data for reading and writing will be enough to take over. after trying to reading again the 28h and 29 h registers i get the results of 20h and 21h (for reading the registers respectively ) after number of clocks, but then the data bus goes to 01h value at finish.  the signals from model-sim:

[Altera_Forum]

Problem solved,but i have other question to ask - what is the mac address of the DE2 ?-> can i configure it by myself ? tried to reset all registers of PHY before accessing and trying to read the first word in the EEPROM . I get the following mac address : 01:00:00:00:00:00 (multicast address) 

is it correct ?!.  I checked also in the de2_net UDP project file that in the header file the address is this: ether_addr[6]={ 0x01, 0x60, 0x6E, 0x11, 0x02, 0x0F } does it works on all ALTERA fpga boards ?   Thx in advance.