05-07-2018 11:11 PM
Hi,I am using Quartus version 17.1. I am receiving this warning message: Warning (12620): Input port OE of I/O output buffer "fx3_dq~output" is not connected, but the atom is driving a bi-directional pin from Quartus while compiling. fx3_dq is 8 bits wide and is an inout wire connected from another module to the top level. Why am I receiving this message? I found this page : https://www.altera.com/support/support-resources/knowledge-base/solutions/rd01262015_264.html but it says this only occurs in version 14.1 and earlier. I also created tried changing the output by assigning it to high if an output enable signal is high and low if low, but I still receive this message. -Thank you
05-08-2018 03:58 AM
Hi,Just implemented logic you have described in both pro & std but not able to get the warning mentioned. 1. Just delete the incremental_db & db folder and try.
- Which edition of Quartus (pro/std) are you using?
- Attach the code & message log from Quartus.
05-08-2018 03:37 PM
I am using Quartus Prime Standard Editionfx3_dq is directly connected to FPGA pins, but is also passed into a module like so: fx3 fx3_inst( .reset(reset) ,.clk(clk) ,.fdata(fx3_dq) ,.sloe(fx3_sloe_n) ..... ); This is just an example and inside the module there is an assign like so for fdata: assign fdata = (slwr_loopback_1d_) ? 8'dz : data_from_hps; The code is the sample project from FX3; I'm not sure if I can post it but I have a link to the page. http://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-interface On my top level do I also need a tri-state as mentioned? Or should the tri-state be taken care of with the assign statement in the module? Thank you
05-08-2018 05:03 PM
--- Quote Start --- You can't have internal tri-states. They can only be at the top level. Is slwr_loopback_1d_ your oe signal? --- Quote End --- Okay, I will move the assign to my top level instead. Is it because tri-states only apply directly to the FPGA pins?