Inserting custom verilog into OpenCL toolflow

[Altera_Forum]

I'm looking to write some custom verilog code and add it to my OpenCL auto-generated Qsys system. 

 The problem is, I want this newly modified system to be generated as a ,aocx file. Is this possible? If so, how do I do it? I'm not sure if separating the commands from AOCL will do this.  I've tried:  aoc -c <mykernel>.cl  then adding in my own code  then: aoc <mykernel>.aoco  Will the aocx generation rely on the modified Quartus project files, or the unmodified aoco?

[Altera_Forum]

After running aoc -c <mykernel>.cl, the corresponding HDL code of your kernel has not been generated yet. So, it is impossible to add custom verilog code.  

 I am also interested in inserting custom verilog into OpenCL toolflow. It is critical to achieve optimum performance.

[Altera_Forum]

Hello, 

 I was wondering if you found a solution to add your custom verilog code to the auto generated design.

[Altera_Forum]

Hello, 

In 15.1 we'll have a feature called "libraries" introduced in early access stage to some customers (and it will go public in 16.0). It will allow packaging custom RTL that behaves similar to OpenCL pipeline (stallable, single clock, streaming interface) into a library of functions. These functions can be called from OpenCL kernels as regular C functions. Their RTL implementation would be automatically stitched into the OpenCL system for you.  Stay tuned!