Integrate AMB into SOPC builder

[Altera_Forum]

Hi, 

 Does someone have an experience on sucessfully implemening IP with AMB I/F into SOPC builder? If you can share a sample design, I really appreciate it.  Regards

[Altera_Forum]

Were you planning on connecting multiple AMB devices together in SOPC Builder? If so, then it would probably be difficult, as SOPC Builder does not support the AMB protocol directly. Qsys is supposed to be supporting extra bus protocols, but you will have to wait. 

 If you are just trying to interface an AMB device to an Avalon bus, then you need to create an AHB-to-Avalon-MM master bridge (for an AHB bus master), or an Avalon-MM slave to AHB bus (to communicate with a peripheral). If you device interface only supports single transaction read/write, then the interface is pretty simple. If you want burst-mode support, then that is also possible, but will involve a little more work.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Thank you so much for your answer. I need single transaction and slave AHB IP. I will consider more by myself.  Regards

[Altera_Forum]

--- Quote Start ---   I need single transaction and slave AHB IP.   --- Quote End ---  This should be very simple to implement.  Start out by creating a simple 'register' design with an Avalon-MM interface. Import that design into SOPC Builder so that you can get the _hw.tcl file needed for the interface. Then the component can be used from within SOPC builder.  Use the Verification IP suite (Avalon-MM master BFM) to test reads and writes, i.e., create an SOPC system with an Avalon-MM master BFM and your new component. Then test is using Modelsim. The Avalon-MM BFM uses SystemVerilog, so your component will need to be in verilog if you are using the free Modelsim-Altera Edition. If you have Modelsim full-edition, then mixed simulation works fine (I use it for VHDL components).  Then you can try to create your AMB interface.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

 Thank you so much for the information.  Regards!

[Altera_Forum]

Hi Dave,  

I'm going to use a LEON cpu with nios2 cpu together on stratix iv. In this regard, I need to have an AHB-to-avalon bridge, by which I establish the communication.  Would you please help me.  Is there any avalon-to-ahb bridge supported in quartes, either in SOPC builder, or Qsys?  Thanks in advance, Hamidreza

[Altera_Forum]

Hi Hamidreza, 

   --- Quote Start ---   I'm going to use a LEON cpu with nios2 cpu together on stratix iv. In this regard, I need to have an AHB-to-avalon bridge, by which I establish the communication.  Would you please help me.    --- Quote End ---  Sure, I'll try :)    --- Quote Start ---   Is there any avalon-to-ahb bridge supported in quartes, either in SOPC builder, or Qsys?   --- Quote End ---  There is not a bridge in Altera's provided IP. In Quartus II version 12.0 there will be AXI4 bridges, however, I doubt they will have support for all AMBA protocols. I'd recommend designing your own AHB-to-Avalon bridge, it shouldn't be too difficult.  1) Set up a LEON simulation in Modelsim 2) Boot the processor and perform a read and write transaction to the external bus 3) Map or convert the transaction into an equivalent Avalon-MM transaction  If the AHB bus implements posted writes and pipelined reads, then you should be able to create the above pretty easily. If the buses are a little more different, then you can use a FIFO to implement the bridge. On one side of the FIFO you have a slave that accepts AHB transactions and writes a read/write command into the FIFO, and then on the other side of the FIFO, you have an Avalon-MM master that reads the command and then issues an Avalon-MM command. You use a FIFO so that the LEON can post writes without having to wait for them to complete on the Avalon-MM slave.  Cheers, Dave

[Altera_Forum]

hi 

 did anyone created this 2 bridges (master and slave) and could provide them?  i would really appreciate that.  best, Tristan

[Altera_Forum]

Hi Tristan, 

  --- Quote Start ---   did anyone created this 2 bridges (master and slave) and could provide them?   --- Quote End ---    I haven't. I've been waiting for the support for AXI4 to be added to Quartus and their Verification IP suite before investing any time in looking at the ARM bus protocols.  Take a look at the latest version of Quartus and see if there is anything new in there. I haven't looked at the latest service pack.  Cheers, Dave

[Altera_Forum]

quartus will add the 2 bridges in the mid of 2013 but thats too late for me thats why i am asking if someone did them and could provide me sources.

[Altera_Forum]

--- Quote Start ---  quartus will add the 2 bridges in the mid of 2013 but thats too late for me thats why i am asking if someone did them and could provide me sources.  --- Quote End ---    Altera recently released SP1 for Quartus 12.1, are there updates on AXI4 support.  Regards Bhargav