Integrate not-ready IP with SOPC builder

[Altera_Forum]

Hi, 

 Does anyone have experience to integrate a MegaCore that is not SOPC builder ready with SOPC builder.  Specifically I'm considering the PCIe soft MegaCore on the Cyclone IV GX. Since the application needs two PCI express port, at least one need to be soft IP.  The MegaCore has Avalon-MM port, so I guess there is some way, similar to integrate user logic into SOPC builder system.  Regards

[Altera_Forum]

Its not too hard to create an SOPC builder component. However, the tools are not very intelligent or user-friendly. So here's a procedure that I have found that gives me enough of a framework to start with; 

 1) Start Quartus 10.1 2) Create a project (otherwise SOPC Builder is greyed out) 3) Start SOPC builder; Tools->SOPC Builder 4) In SOPC Builder select; File->New Component  This starts the component editor. This interface is good enough to get started, but its not perfect.   For example, on the 'HDL Files' tab, you can add an existing file, eg. VHDL or Verilog, and Quartus will process the file and try to guess the interfaces. Since VHDL can depend on libraries, the elaboration process used by Quartus will fail (unless you add the libraries required). For VHDL, I find the process is easier if I just use the GUI to create example interfaces (code stubs), and then use that as the basis for my custom design.  Lets say you want to just 'see' how things work. If you click on the 'Signals' you will see it is empty (assuming you did not import an HDL file). At the top of this GUI, the 'Templates' menu gives you the option of adding interfaces. Eg. click on Templates->Add Typical Avalon-MM slave, and a slave called s0 will be added, as will a clock and reset interface. The signal naming convention of the template is that the signals are prefixed with avs_s0, where s0 is the slave interface. This s0 will show up in the SOPC builder connections diagram. You can rename this interface by clicking on the 'Interfaces' tab, and renaming it 'slave', or 'mm_slave'. If you only have one slave interface, go back to the 'Signals' tab and remove the s0 from the signal names.  Then click on the 'Library Info' tab, and enter something in the 'Group', 'Description', and 'Created by' fields. By putting text in these fields, you ensure that they show up in the generated _hw.tcl file.  Click on the 'HDL files' tab, and click on 'Create HDL Template'. Select 'Verilog' or 'VHDL', and then click 'Save'.  Now click 'Finish' and save the files.  This gives you new_component.vhd (or .v) and new_component_hw.tcl.  Download the SOPC Builder Users Guide and look at the _hw.tcl file in conjunction with Chapter 7. You'll also want the Avalon Interface Specification, as it has tables of properties that are used in the _hw.tcl file.  The key point of this procedure is that it gives you a starting point, i.e., an HDL file and a corresponding _hw.tcl file that SOPC Builder will recognize.  I find that _hw.tcl has some 'extra' Tcl parameters that are not required, or documented. To determine if they are needed or not, I get a design to synthesize and simulate, and then start deleting parameters. If it doesn't break, I figure they cannot be important :)  Cheers, Dave

[Altera_Forum]

Hello Dave, 

 I appreciate your detailed explanation. I will try.  Regards,