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LKwia
Beginner
1,370 Views

Intel HLS 17.1 verilog code generation error.

If I have such a declaration of function:

"hls_avalon_slave_component component 

void hls_aes256(hls_avalon_slave_memory_argument(1) uint8_t *control,

             hls_avalon_slave_memory_argument(32) uint8_t *key,

             hls_avalon_slave_memory_argument(16) uint8_t *in_data,

             hls_avalon_slave_memory_argument(16) uint8_t *out_data)"

 

why it generates verilog in the code:

"module hls_aes256_internal

(

  input logic clock,

  input logic resetn,

  input logic clock2x,

  output logic done_irq,

  // AVS avs_control

  input logic avs_control_enable,

  input logic avs_control_read,

  input logic avs_control_write,

  input logic avs_control_address,

  input logic [7:0] avs_control_writedata,

  input logic avs_control_byteenable,

  output logic [7:0] avs_control_readdata,

  output logic avs_control_readdatavalid,

  // AVS avs_cra

  input logic avs_cra_enable,

  input logic avs_cra_read,

  input logic avs_cra_write,

  input logic [1:0] avs_cra_address,

  input logic [63:0] avs_cra_writedata,

  input logic [7:0] avs_cra_byteenable,

  output logic [63:0] avs_cra_readdata,

  output logic avs_cra_readdatavalid,

  // AVS avs_in_data

  input logic avs_in_data_enable,

  input logic avs_in_data_read,

  input logic avs_in_data_write,

  input logic avs_in_data_address,

  input logic [127:0] avs_in_data_writedata,

  input logic [15:0] avs_in_data_byteenable,

  output logic [127:0] avs_in_data_readdata,

  output logic avs_in_data_readdatavalid,

  // AVS avs_key

  input logic avs_key_enable,

  input logic avs_key_read,

  input logic avs_key_write,

  input logic [2:0] avs_key_address,

  input logic [31:0] avs_key_writedata,

  input logic [3:0] avs_key_byteenable,

  output logic [31:0] avs_key_readdata,

  output logic avs_key_readdatavalid,

  // AVS avs_out_data

  input logic avs_out_data_enable,

  input logic avs_out_data_read,

  input logic avs_out_data_write,

  input logic [2:0] avs_out_data_address,

  input logic [15:0] avs_out_data_writedata,

  input logic [1:0] avs_out_data_byteenable,

  output logic [15:0] avs_out_data_readdata,

  output logic avs_out_data_readdatavalid

);"

0 Kudos
12 Replies
78 Views

@LKwia​ 

Hi,

I am looking at this thread, I am not sure if I understand you correctly.

Are you asking why HLS generate Verilog code ? or is there any problem in generated code ? Please specify.

 

HLS is intended to generate the HDL code (Verilog) in this case, that can be used later in Quartus to generate programming file or to integrate with rest of your design.

 

You might want to take a look at our HLS web page.

https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html

 

Thanks,

Arslan

LKwia
Beginner
78 Views

If I have a port declaration "hls_avalon_slave_memory_argument(16) uint8_t *in_data" then I should get a:

// AVS avs_in_data

  input logic avs_in_data_enable,

  input logic avs_in_data_read,

  input logic avs_in_data_write,

  input logic [3:0] avs_in_data_address,

  input logic [7:0] avs_in_data_writedata,

  input logic avs_in_data_byteenable,

  output logic [7:0] avs_in_data_readdata,

  output logic avs_in_data_readdatavalid.

78 Views

Hi,

Can you confirm the version of HLS you are using ?

Also which OS Windows / Linux ?

 

Thanks,

Arslan

LKwia
Beginner
78 Views

Quartus Prime 17.1.0 Build 590 Standard Edition, Windows 10 64bit.

LKwia
Beginner
78 Views

I wrote aes in opencl, but in program "Intel® FPGA SDK for OpenCL 17.1 (aoc)" also generates errors.

 

set AOCL_BOARD_PACKAGE_ROOT=C:\intelFPGA\17.1\hld\board\c5soc

aoc -g0 -board=c5soc_sharedonly aes256.cl -o aes256

 

I will not upgrade to newer software (Quartus v18.0) because it has an unstable synthesis.

 

And now a very important question will appear:

Is it in your company, in addition to marketing, something does it still normally works ?

 

HRZ
Valued Contributor II
78 Views

I cannot comment on your HLS problem but the OpenCL compilation is not working because of this error:

 

C:/Users/user/Desktop/OpenCL_AES/aes256/system/synthesis/submodules/acl_fifo_stall_valid_lookahead.sv Line: 25

Error (10759): Verilog HDL error at aes256_system.v(311): object aes256Encrypt_finish declared in a list of port declarations cannot be redeclared within the module body File: C:/Users/user/Desktop/OpenCL_AES/aes256/system/synthesis/submodules/aes256_system.v Line: 311

 

Are you using an HDL library in the OpenCL code? I don't see why you would get such error with a standard OpenCL design.

LKwia
Beginner
78 Views

I'm not using additional HDL library, "aoc" generates errors.

78 Views

Hi @LKwia​ 

 

Indeed what you quoted as HLS output is incorrect.

 

I have tried to create a similar component on my HLS 18.1 Standard Edition Windows 10, I got the correct output (dsee code snippets below).

 

My suggestion to you will be to update to latest version.

 

C++ Component Definition:

component void hls_aes256( hls_avalon_slave_memory_argument(1) uint8_t *control, hls_avalon_slave_memory_argument(32) uint8_t *key, hls_avalon_slave_memory_argument(16) uint8_t *in_data, hls_avalon_slave_memory_argument(16) uint8_t *out_data, int N )

Verilog Output:

// Generated by Intel(R) HLS Compiler, Version 18.1.0 Build 625   ///////////////////////////////////////////////////////////////// // MODULE hls_aes256_internal /////////////////////////////////////////////////////////////////   module hls_aes256_internal ( input logic clock, input logic resetn, input logic [31:0] N, input logic start, output logic busy, output logic done, input logic stall, // AVS avs_control input logic avs_control_enable, input logic avs_control_read, input logic avs_control_write, input logic avs_control_address, input logic [7:0] avs_control_writedata, input logic avs_control_byteenable, output logic [7:0] avs_control_readdata, output logic avs_control_readdatavalid, // AVS avs_in_data input logic avs_in_data_enable, input logic avs_in_data_read, input logic avs_in_data_write, input logic [3:0] avs_in_data_address, input logic [7:0] avs_in_data_writedata, input logic avs_in_data_byteenable, output logic [7:0] avs_in_data_readdata, output logic avs_in_data_readdatavalid, // AVS avs_key input logic avs_key_enable, input logic avs_key_read, input logic avs_key_write, input logic [4:0] avs_key_address, input logic [7:0] avs_key_writedata, input logic avs_key_byteenable, output logic [7:0] avs_key_readdata, output logic avs_key_readdatavalid, // AVS avs_out_data input logic avs_out_data_enable, input logic avs_out_data_read, input logic avs_out_data_write, input logic [3:0] avs_out_data_address, input logic [7:0] avs_out_data_writedata, input logic avs_out_data_byteenable, output logic [7:0] avs_out_data_readdata, output logic avs_out_data_readdatavalid );

Thanks,

Arslan

LKwia
Beginner
78 Views

I do not know what you did, that it works well.

But with me it works the same way.

 

 

// Generated by Intel(R) HLS Compiler, Version 18.1.0 Build 625

 

/////////////////////////////////////////////////////////////////

// MODULE hls_aes256_internal

/////////////////////////////////////////////////////////////////

module hls_aes256_internal

(

  input logic clock,

  input logic resetn,

  input logic clock2x,

  output logic done_irq,

  // AVS avs_control

  input logic avs_control_enable,

  input logic avs_control_read,

  input logic avs_control_write,

  input logic avs_control_address,

  input logic [7:0] avs_control_writedata,

  input logic avs_control_byteenable,

  output logic [7:0] avs_control_readdata,

  output logic avs_control_readdatavalid,

  // AVS avs_cra

  input logic avs_cra_enable,

  input logic avs_cra_read,

  input logic avs_cra_write,

  input logic [1:0] avs_cra_address,

  input logic [63:0] avs_cra_writedata,

  input logic [7:0] avs_cra_byteenable,

  output logic [63:0] avs_cra_readdata,

  output logic avs_cra_readdatavalid,

  // AVS avs_in_data

  input logic avs_in_data_enable,

  input logic avs_in_data_read,

  input logic avs_in_data_write,

  input logic avs_in_data_address,

  input logic [127:0] avs_in_data_writedata,

  input logic [15:0] avs_in_data_byteenable,

  output logic [127:0] avs_in_data_readdata,

  output logic avs_in_data_readdatavalid,

  // AVS avs_key

  input logic avs_key_enable,

  input logic avs_key_read,

  input logic avs_key_write,

  input logic [2:0] avs_key_address,

  input logic [31:0] avs_key_writedata,

  input logic [3:0] avs_key_byteenable,

  output logic [31:0] avs_key_readdata,

  output logic avs_key_readdatavalid,

  // AVS avs_out_data

  input logic avs_out_data_enable,

  input logic avs_out_data_read,

  input logic avs_out_data_write,

  input logic [2:0] avs_out_data_address,

  input logic [15:0] avs_out_data_writedata,

  input logic [1:0] avs_out_data_byteenable,

  output logic [15:0] avs_out_data_readdata,

  output logic avs_out_data_readdatavalid

);

 

78 Views

How about sharing your .cpp file ?

LKwia
Beginner
78 Views

Unfortunately, I can't.

78 Views

I hope using the example I shared with you in separate message helped you to proceed.

 

Example is using the same component definition as you shared in the thread and it generates the correct HLS output.

 

Thanks,

Arslan

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