Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,047 Views

Interfaces and Synthesis

I am trying to use interfaces for use in abstraction and simplification of port connections. Something structs cannot do very well because they cannot carry information about direction. However, I cannot quite understand how an 'interface' interfaces to a top level file's ports. 

 

Here is an example of some code I was testing with to try understanding interfaces. 

// Interface definition interface EMIF_Bus; input logic EMIF_addr; output logic EMIF_data; input logic EMIF_readEnable; endinterface // Top level module interface_top ( input clk, input reset, EMIF_Bus chip_io ); // Instantiating lower module interface_sv SYSTEMVERILOG_DUT ( .clk (clk), .reset (reset), .module_io (chip_io) );  

The following is an example of a dummy top level file for a quartus project. The submodule will assign an appropriate output depending upon address and read, but the important part is that this is synthesize without errors and through the technology map viewer I can verify it would function. The issue I did not expect is the dozens of warnings for permanently forcing tristate buffers as inputs or outputs. My understanding is that the declaration of "input" or "output" in the interface should remove the underlying notion of "inout" that is default for an signal that would not have a direction. However, the warnings would indicate that these port connections are being treated as "inout" rather than simply output or input. 

 

Therefore, I am trying to clarify my misunderstanding of interfaces.
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
21 Views

I've never used this before, but this tutorial does not show directions for the signals in the interface definitions: 

 

https://www.doulos.com/knowhow/sysverilog/tutorial/interfaces/
Altera_Forum
Honored Contributor I
21 Views

Looking back on the sources I have used on this topic I misunderstood and botched the syntax. It should have looked like this. 

 

interface EMIF_Bus ( input wire EMIF_addr, output logic EMIF_data, input wire EMIF_readEnable ); endinterface module interface_top ( input clk, input reset, input addr, output data, input readEnable ); EMIF_Bus module_io ( .EMIF_addr (addr), .EMIF_data (data), .EMIF_readEnable (readEnable) ); interface_sv SYSTEMVERILOG_DUT ( .clk (clk), .reset (reset), .module_io (module_io) );  

The above interface definition allows for external variables and nets to be connected to the interface. However, it requires a declaration and connection of external variables/nets to the interface. From there any module sharing this declared interface will have access to these signals. So, this solves the issue.
Reply