Internal Error: Sub-system: CDB_SGATE, File: /quartus/db/cdb_sgate/cdb_sgate_component.cpp, Line: 93

[sukesh]

Hi, I am working on Quartus Prime pro 20.3 version. The Device I am working with is Arria10. I am facing the internal error while compiling the project. The Analysis and Synthesis runs initially after reaching a particular percentage of compilation a pop-up window indicating following errors.

Problem Details
Error:
Internal Error: Sub-system: CDB_SGATE, File: /quartus/db/cdb_sgate/cdb_sgate_component.cpp, Line: 931
Port direction does not agree.
Stack Trace:
Quartus 0x7011b: CDB_SGATE_COMPONENT::retrieve_known_port + 0x23b (db_cdb_sgate)
Quartus 0x5eeb8: qis_get_component_ports + 0x118 (synth_qis)
Quartus 0x5bcba: QIS_RTL_STAGE::IMPL::merge_nodes + 0x6ba (synth_qis)
Quartus 0x5c7be: QIS_RTL_STAGE::IMPL::merge_sgate_models + 0x36e (synth_qis)
Quartus 0x56f52: QIS_RTL_STAGE::IMPL::dissolve_partition + 0x3b2 (synth_qis)
Quartus 0x66ff0: QIS_RTL_STAGE::IMPL::uniquify + 0x9f0 (synth_qis)
Quartus 0x68108: QIS_RTL_STAGE::IMPL::uniquify + 0xc38 (synth_qis)
Quartus 0x21c8d: qis_uniquify + 0x1ed (synth_qis)
Quartus 0x16442: TclNRRunCallbacks + 0x62 (tcl86)
Quartus 0x17c4d: TclEvalEx + 0x9ed (tcl86)
Quartus 0xa6a8b: Tcl_FSEvalFileEx + 0x22b (tcl86)
Quartus 0xa5136: Tcl_EvalFile + 0x36 (tcl86)
Quartus 0x15246: qexe_evaluate_tcl_script + 0x4e6 (comp_qexe)
Quartus 0x1413b: qexe_do_tcl + 0x46b (comp_qexe)
Quartus 0x1a70e: qexe_run_tcl_option + 0x5ee (comp_qexe)
Quartus 0x146b1: QCU::DETAIL::intialise_qhd_and_run_qexe + 0xa1 (comp_qcu)
Quartus 0x1f8d2: qcu_run_tcl_option + 0x2f2 (comp_qcu)
Quartus 0x12cc: qsyn2_tcl_process_default_flow_option + 0x1dc (quartus_syn)
Quartus 0x1a00b: qexe_run + 0x3eb (comp_qexe)
Quartus 0x1b14a: qexe_standard_main + 0x26a (comp_qexe)
Quartus 0x2fe9: qsyn2_main + 0x129 (quartus_syn)
Quartus 0x167e8: msg_main_thread + 0x18 (CCL_MSG)
Quartus 0x17001: msg_thread_wrapper + 0x71 (CCL_MSG)
Quartus 0x21610: mem_thread_wrapper + 0x70 (ccl_mem)
Quartus 0x14b7d: msg_exe_main + 0x20d (CCL_MSG)
Quartus 0x4c38: __scrt_common_main_seh + 0x11c (quartus_syn)
Quartus 0x17613: BaseThreadInitThunk + 0x13 (KERNEL32)
Quartus 0x526a0: RtlUserThreadStart + 0x20 (ntdll)

End-trace

Executable: qpro
Comment:
None

System Information
Platform: windows64
OS name: Windows 10
OS version: 10.0

Quartus Prime Information
Address bits: 64
Version: 20.3.0
Build: 158
Edition: Pro Edition

Kindly help me find the issue here. I am not sure whether it is due to HDL Error (but I did not see any errors in message window, but synthesis fails) or a system issue?

Thanks in advance.

[RichardTanSY_Intel]

I haven't seen this internal error before. Could you help to share your design .qar file (Project> Achieve Project) that could duplicate this error?

We will need to duplicate the error as without the error duplication from our side, it would be hard to find a workaround/solution.

If possible, try to upgrade to the latest Quartus Pro version 22.4 to check if the issue persists, as a lot of bug has been fixed since then.

I found a similar thread but not sure if it helps.

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Quartus-Prime-Pro-19-2-quits-unexpected-with-following-error/m-p/646439

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.

[sukesh]

Hi Richard,

Attaching the archived project for your reference.

[RichardTanSY_Intel]

I upgraded the design to Quartus 22.4 (with IP upgraded) and no IE occur anymore but error pop up at Analysis & Synthesis instead.

Error: REFCLK port on the PLL is not properly connected on instance i_M_MarlinHps|mm_video_mux|mm_video_mux|lcd_lvds_inst|lcd_lvds|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll. This refclk port on the PLL must be connected. 

Info: Must be connected 

Error: RST_N port on the PLL is not properly connected on instance i_M_MarlinHps|mm_video_mux|mm_video_mux|lcd_lvds_inst|lcd_lvds|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll. The reset port on the PLL must be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock. 

Info: Must be connected 

Try to upgrade your design and see if the IE has gone.

Best Regards,

Richard Tan

[sukesh]

Hi Richard,

Thank you for this update. Will check on those errors.

I think 22.4 upgrade is helping it route the Internal errors on to the message window. 

Thanks,

Sukesh

[RichardTanSY_Intel]

Since the IE has been resolved, I now transition this thread to community support. 

Feel free to open a new thread if you have further questions.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.