Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/vhdl/vhdlname_ela

Altera_Forum · ‎04-24-2014

When I was trying to synthesize following code:

process(CLK)

begin

if rising_edge(CLK) then

case find_1st_bit is

when first =>

if add2_finish = '1' then

cnt0 <= 0;

cnt2 <= 0;

find_1st_bit <= second;

else

find_1st_bit <= first;

end if;

when second =>

cnt0 <= cnt0 + 1;

TRAM(cnt0) <= RAM3(cnt0);

if cnt0 = 43 then

cnt0 <= 0;

cnt1 <= 15;

find_1st_bit <= third;

else

find_1st_bit <= second;

end if;

when third =>

if (TRAM(43)(15) = '0') then

cnt0 <= 43; cnt2 <= 43;

find_1st_bit <= fourth;

else

cnt1 <= 0;

find_1st_bit <= first;

end if;

when fourth =>

if cnt0 = 0 then

TRAM(cnt0) <= TRAM(cnt2)(15 downto 1) & '0';

cnt1 <= cnt1 - 1;

cnt0 <= 0; cnt2 <= 0;

find_1st_bit <= third;

else

cnt0 <= cnt0 - 1;

cnt2 <= cnt2 - 1;

TRAM(cnt0) <= TRAM(cnt2)(14 downto 0) & RAM3(cnt2-1)(cnt1);

find_1st_bit <= fourth;

end if;

when others => null;

end case;

end if;

end process;

I've got following message. Compilation in modelsim done well. Please help me to solve this problem.

Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/vhdl/vhdlname_elab.cpp, Line: 1491dim + 1 < indices->Size()

Stack Trace:

0x38e90: vrfx_altera_assert + 0x20 (synth_vrfx)

0x1d305d: VhdlName::EvaluatePartial + 0x25d (synth_vrfx)

0x1d4fc1: VhdlIdRef::EvaluateName + 0x481 (synth_vrfx)

0x1d5680: VhdlIndexedName::EvaluateName + 0x440 (synth_vrfx)

0x1a0eaa: VhdlName::Evaluate + 0x1a (synth_vrfx)

0x1dd302: VhdlSignalAssignmentStatement::Execute + 0xd2 (synth_vrfx)

0x1d8c54: VhdlCaseStatementAlternative::ExecuteAlternative + 0x34 (synth_vrfx)

0x1e1495: VhdlCaseStatement::Execute + 0x535 (synth_vrfx)

0x1dc880: VhdlIfStatement::Execute + 0x3b0 (synth_vrfx)

0x1dd821: VhdlProcessStatement::Execute + 0x1d1 (synth_vrfx)

0x159b03: VhdlArchitectureBody::Elaborate + 0xd3 (synth_vrfx)

0x15d93b: VhdlEntityDecl::CoreElaborate + 0x42b (synth_vrfx)

0x15e00e: VhdlEntityDecl::Elaborate + 0x37e (synth_vrfx)

0x5169e: VRFX_VERIFIC_VHDL_ELABORATOR::elaborate + 0x1be (synth_vrfx)

0x4c3c6: VRFX_ELABORATOR::elaborate + 0xc6 (synth_vrfx)

0x9cb71: SGN_FN_LIB::elaborate + 0x131 (synth_sgn)

0x9f2fa: SGN_FN_LIB::start_vrf_flow + 0xa (synth_sgn)

0xa0627: SGN_FN_LIB::start + 0x597 (synth_sgn)

0x7dd79: SGN_EXTRACTOR::single_module_extraction + 0x149 (synth_sgn)

0x8264e: SGN_EXTRACTOR::recursive_extraction + 0x15e (synth_sgn)

0x8098b: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist + 0x2db (synth_sgn)

0x8268f: SGN_EXTRACTOR::recursive_extraction + 0x19f (synth_sgn)

0x8098b: SGN_EXTRACTOR::recurse_into_newly_extracted_netlist + 0x2db (synth_sgn)

0x8268f: SGN_EXTRACTOR::recursive_extraction + 0x19f (synth_sgn)

0x85d4a: SGN_EXTRACTOR::extract + 0x16a (synth_sgn)

0xd118: sgn_qic_full + 0x138 (synth_sgn)

0x39cb: qsyn_execute_sgn + 0xeb (quartus_map)

0x19f2b: QSYN_FRAMEWORK::execute_core + 0x8b (quartus_map)

0x1c930: QSYN_FRAMEWORK::execute + 0xa0 (quartus_map)

0xf211: qexe_get_command_line + 0x1461 (comp_qexe)

0x116b7: qexe_process_cmdline_arguments + 0x387 (comp_qexe)

0x117a4: qexe_standard_main + 0x84 (comp_qexe)

0x17ede: qsyn_main + 0x5e (quartus_map)

0x1b91: msg_main_thread + 0x11 (CCL_MSG)

0x1be8: _thr_final_wrapper + 0x8 (ccl_thr)

0x1b05: msg_thread_wrapper + 0x85 (CCL_MSG)

0x218a: mem_thread_wrapper + 0x4a (ccl_mem)

0x28a03: msg_exe_main + 0x63 (CCL_MSG)

0x1938c: _main + 0x1c (quartus_map)

0x24ab4: __ftol2 + 0x1ce (quartus_map)

0x17076: RegisterWaitForInputIdle + 0x48 (kernel32)

End-trace

Quartus II Version 11.0 Build 157 04/27/2011 SJ Full Version

Altera_Forum · ‎04-24-2014

Without examine the code in detail I'd like to as if it would be possible for you to try to compile this design in a newer version of Quartus than 11.0? I would expect such an internal error to be fixed by now if it is indeed something in the code that generates it.

Altera_Forum · ‎04-24-2014

Looking into the code, my guess is that it is the index to RAM3 in the fourth case that might trick the mapper into believing that it could possibly go out of range. What happens if you try to compile with that line looking like this instead:

TRAM(cnt0) <= TRAM(cnt2)(14 downto 0) & RAM3(cnt2)(cnt1);

I understand that it will render a functional bug, I would just compile with this to see if that is what causing Quartus to error out.

Altera_Forum · ‎04-29-2014

Thank you very much for reply. I solved this problem by assigning RAM elements to another additional signal. Thanks a lot again.