Intrroducing delay at pin level

[Altera_Forum]

Hello All, 

 I am new to the Quartus tool, I just need your help to solve my doubts.  I wanted to that "How to introduce output delay at pin level"  Example: I have two input signals inp1, inp2 and two output signal op1 , op2  op1 <= not inp1; op2 <= not inp2;  So if you see both outputs behaves same way., because the are implemented using not gate..  Now I need let say 10 ns more delay at op2 compare to op1 on the real hard ware..  So achieve this what kind of constraints I have to give.  Thanks in advance Pavan M

[Altera_Forum]

I suggest you to use a synchronous approach to this problem. You should use a clock with period equal to the desired delay and use a simple VHDL block to produce the output after a clock edge. 

The asynchronous solutions are always less reliable than the synchronous ones, so I don't recommend you to use them.

[Altera_Forum]

Yes; I do agree with your answer. But In this case op1 and op2 are going to the buffer chip as enable and direction. Here the generation of the op1 and op2 shall be independent of clock. Its a requirement, so I cannot use the clock to do this. op1 is going as enable to the data buffer, op2 is going as direction to the data buffer. Now first i have to set the direction and then I have to give the enable. the delay between these shall be at least 5 ns.

[Altera_Forum]

Why can't you use a clock for introducing this delay?  

:confused:

[Altera_Forum]

I cant use clock, because its a requirement. Clock shall not be used to generate the enable signals to the Data buffer. 

 Here in my case clock is coming for other board1 and the inp1, inp2 are coming from other board2, and op1 and op2 are going to the board3. thats why I should not generates the enable for board3 which is dependent on board1

[Altera_Forum]

http://www.alteraforum.com/forum/showthread.php?t=3028&highlight=paths 

 Make sure you understand the min corner timing model, as that's where this is going to be an issue under worst case conditions.

[Altera_Forum]

I don't think, that timing driven place and route will give a sufficient delay amount. You possibly have to use additional logic cells that are protected by a keep synthesis attribute. 

 See e. g. http://www.alteraforum.com/forum/showthread.php?t=2418

[Altera_Forum]

I've seen some designs with pretty large hold requirements, whereby Quartus has properly added many nanoseconds of delay(don't remember the exact number, but I think it was around 5ns). Looking in the chip-editor, it was routed all over the place to connect to cells that were right next to each other. So it did a good job, and I wouldn't automatically assume that Quartus couldn't do it with timing constraints alone.

[Altera_Forum]

The requirement in the first post was 10 ns, and that's probably too much. I agree, that for smaller delays, one should try with timing constraints first. 

 The point is, that timing constraints never cause the compiler to add additional delay elements (except for using the rather small programmable I/O delay), they only cause a variation of the predefined routing. So the available range of timing adjustment depends on the routing delay that already exists in the design. It may be rather large for a complex, distributed design or small for a compact design.  In my understanding, the purpose of timing constraints is mainly to assure the correct design implementation considering logic element, I/O and routing delays. They are not intended to introduce arbitrary delays.

[Altera_Forum]

A positive hold requirement is meant to introduce delays. (Ideally we want to design where the fitter doesn't have to do this, but I've seen enough examples that it is useful). And in reality, he'll have to put in Timing Constraints first to ever know if that 10ns requirement is being met. I have seen the router go halfway across the chip and then back again, just to add delays to two nodes right next to each other, so it does do more than IO delays or small adjustments of existing routes. I figure it's worth a shot, but agree there's a "niceness" to adding a physical delay chain made of LUTs.

[Altera_Forum]

Rather than being academic, I threw down a design with 4pins. I made the fast path have a max delay of 8ns. The delayed path had a min delay of 18ns and a max delay of 30ns. 

 Quartus did an excellent job routing the signal back and forth across the EPC3 device, giving us a cumulative delay on a single route of 25ns, so at the max timing model, it barely met that 30ns setup requirement. That being said, it still missed the min by a few nanoseconds. So I got rid of the max_delay requirement and reran, and it met timing. So the fitter did a quite impressive job.  Of course, I'm mixing timing models in this simplistic methodology, which isn't accurate. I'd really want to make one of the pins look like a clock, so I can relate the other path to it. Or just make sure the delay is greater than 10ns by visually comparing at the two timing models.

[Altera_Forum]

Hell everybody, 

 thanks a lot for your kind support. As I am new to the quartus I understood some of your answers. I will work it out with your suggestions and I will ask you if I have any thing else. You can update me if you have new solutions for this. Regards Pavan M

[Altera_Forum]

Thank you for the instructive examples! I see, that I underestimated Quartus capabilities in this point.