Inverted global clock generation in MAX V 5M40Z CPLD

[Altera_Forum]

I want to do a simple task:  

Create an inverted version of the external 100MHz clock entering into GCLK Pin-42,  and put that inverted clock onto another GCLK line of the 4 available global clock-lines in MAX V 5M40Z CPLD. (The inverted global clock will drive SDRAM control signals on the rising edge of negated-clock, that's how I want to emulate 'negedge' triggered flipflops in this chip with small resource usage. This way I ensure setup-time of 5ns for SDRAM control & data signals till the normal 'clk' triggers SDRAM operations on its positive edge.)  So essentially I want an internally generated signal 'neg_clk' to become a global clock.   I use these rows in my pin-assignment tcl file to tell Quartus I need it as global signal: set_location_assignment PIN_40 -to neg_clk set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to neg_clk  Seems simple, but whatever I assign (dedicated GCLK pin, "GLOBAL_SIGNAL"),  Quartus seems to refuse/ignore, when I check fitter report: ... +---------------------------------------------------------------------------------------------+ ; Ignored Assignments ; +---------------+----------------+--------------+------------+---------------+----------------+ ; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; +---------------+----------------+--------------+------------+---------------+----------------+ ; Global Signal ; blabla ; ; neg_clk ; GLOBAL CLOCK ; QSF Assignment ; +---------------+----------------+--------------+------------+---------------+----------------+ ...  The problem is, when I use an always '@(posedge neg_clk)' block just with a little arithmetic adder/incrementer circuitry, timing report says fmax is around 30MHz, while with the normal clk on GCLK line it can reach around 70MHz. (Which is still less than the wished 100MHz, but that's another topic.)  Can someone tell me what I might need to further adjust/modify to get 'neg_clk' on a GCLK global resource in the chip? I hope eventually Quartus will understand somehow what I exactly want... (in command-line)  Thanks in advance for replies