Is a Test bench needed for simulation?

[Altera_Forum]

Hello All, 

 I'm new to ModelSim, so please forgive the newbieness. I followed chapter 3 of the ModelSim Tutorial pdf, and all was right in the world. However, I'm a bit confused about the testbench file in the example (tcounter.vhd). From what I understand the testbench file tells ModelSim what the inputs are doing, then ModelSim takes these inputs applies them to the counter.vhd file and spits out an output. Please tell me if I have that right.  If I do have it right, could someone give me an idea where I can read about making a testbench file for a particular .vhd file. I checked the ModelSim tutorial and they only seem to discuss it for Native Link. I also checked the Intro to Quartus and that was a No Go too. I'm using the ModelSim student addition.  Thanks

[Altera_Forum]

Hi Red, 

 Yes, of course you need testbench in order to simulate your design,   I usually don't create my own testbench, I make Quartus generate the testbench. To make Quartus generate a testbench, you need a Vector Waveform File which already has an input stimulus, creating input in Quartus Simulator is easy, just click, click and click, after that export the vwf file to vht (File->Export from Quartus Menu). And in order to simulate in ModelSim correctly based on vwf fille here are the step :   1. Export vwf to vht : File -> Export 2. Make Quartus compile this testbench : Assigments -> EDA Tool Settings, on the NativeLink Setting on Simulation tab, select Compile test bench, and then press Test Benches button. 3. A dialog open, click new and then fill the Test Bench name, and etc... and don't forget to add the vht file. 4. Last, Run the ModelSim from Quartus, Tools -> Run Eda Simulation Tool -> EDA RTL Simulation (for Functional Simulation) or EDA Gate Level (for timing simulation) 5. Done, waveform should be appear...   Hope it can help you... ;)

[Altera_Forum]

You will always need a testbench file. The great thing about testbenches is you can do many many things you couldnt do in synthesizable code, things like time references  

 eg: signal clk : std_logic := '0';  clk <= not clk after 10ns; -- a 100MHz clock  nice convoluted wait statements in processes: eg. wait until rising_edge(clk) and output_valid = '1';  File IO, especially useful for writing log files:  file op_log : text open write_mode is "mylog.log"; variable opline : line; ... write(line, string'("HELLO WORLD!")); writeline(op_log, line);   and then other stuff like pointers, protected types, random number generation and all the signal attributes that can be useful for waiting on (like 'event, 'transaction, 'delayed etc).  Creating a testbench from a waveform file gives you limited scope on what you're actually testing, and normally doesnt give you much scope for full random testing. If you're interested in testbench theory, get hold of a copy of "Writing testbenches: Functional verification of HDL models" by Janick Bergeron. It isnt all in VHDL, but its mostly about the theory of testing and methodologies.

[Altera_Forum]

Thanks Rochmadp, 

 I now have a ghetto divider simulated. However, i had to add the inputs manually, which was a rather big pain. I added the the waves I wanted to the vwt file before I exported the vwt file. However, I think I might be doing something wrong on step 3 of your instructions.  When it asks for the name of the Top level design module in the test bench I assumed it was referring to the Entity name , and when it asked for the design instance i put in the architecture name. Did i make the right assumptions, or have i got (yet again) a case of the newb?  Thanks for your help.

[Altera_Forum]

Hmm,.. try this : 

Top Level Module name : entityname_vhd_vec_tst Design instance name : entityname_vhd_vec_tst   Recompile, and rerun EDA simulation...   I tried like that, and it's work, but honestly I don't know why the name must be like that, I wonder if I could change that name into simpler name, so it will save space in ModelSim Wave window...   Hope it can help you... :)

[Altera_Forum]

Tricky, 

 thank you for the book recommendation. Although the method Rochmadp gave me yielded quick results i want more control, and i don't mind learning a bit more code.   In the exercise in the ModelSim tutorial both the files placed in the work directory (counter.vhd, and tcounter.vhd) are vhd files and as you step through the code you can see the debugger stepping through the tcounter file. I want to be able to do this myself: make a vhd "input" file like the one in this example. Before I go Google crazy do you know of any pdf files that could help me out?  Just something to give me a down and dirty really.  Thanks for your help.

[Altera_Forum]

Well, that gave me an error and an indefinite pause, so big "no go".  

 Thanks though

[Altera_Forum]

Hmm,.. Sorry red, I used "vhd" because I used VHDL as HDL, I don't know if use another HDL, you can find the exact file name at "simulation -> modelsim -> rtl_work" folder under your project folder, it is represented by a folder name.  

 In my case, I found entityname_vhd_vec_tst as an entity at entityname.vht file.   It work fine on me...