In our FPGA project, we instantiate a NIOS and connect a custom_instr_floating_point block to the NIOS for floating calculation speed-up.
But after adding the floating point calculation block, there are some timing violations related with it. Without this block, there is no timing violation issues with the other logics.
From the description of the Floating Point Hardware 2, 5 clock cycles, 4 clock cycles and 16 cycles are needed for the add/substract, multiply and divide operations separately . I am not sure if there is need to add the "set_multicycle_path " timing constraint for the Floating Point Hardware block? If so, how to constraint this block?
Any suggestion appreciated!
There is example how to run the constraint set multicycle path via link below. Could be useful if you are running the source and destination clock at different speed.
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