Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Is it necessary to add timing constraint for the nios_custom_instr_floating_point_2?

ScottHu2021
Beginner
181 Views

Hi,

 

In our FPGA project, we instantiate a NIOS and connect a custom_instr_floating_point block to the NIOS for floating calculation speed-up.

But after adding the floating point calculation block, there are some timing violations related with it. Without this block, there is no timing violation issues with the other logics.

From the description of the Floating Point Hardware 2,  5 clock cycles, 4 clock cycles and 16 cycles are needed for the add/substract, multiply and divide operations separately . I am not sure if there is need to add the "set_multicycle_path " timing constraint for the Floating Point Hardware block?  If so, how to constraint this block?

 

Any suggestion appreciated!

 

Scott

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3 Replies
SyafieqS
Moderator
147 Views

Scott,


There is example how to run the constraint set multicycle path via link below. Could be useful if you are running the source and destination clock at different speed.

https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/tafs/tafs/tcl_p...


SyafieqS
Moderator
129 Views

Scott,


May I know if there is any update?


SyafieqS
Moderator
124 Views

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.


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