Is it possible to force all I/O HighZ before programming (CPLD Max_V)

[JTixi]

On our circuit board, the TDO line as been linked through another I/O pin which is not used in the project (BGA 100 package). The ​first programmation was good. However the unused I/O are linked to ground (why is it the default configuration in Quartus assignment?). It is no more possible to programm the device again, as the TDO is now connected to GND. It seems possible to place all I/O in HighZ mode using the JTAG chain debugger and instruction 0x0B. But this is not kept for further instruction. Do you have an idea or I place the board in rubish box ? Or is it possible to send program file without TDO checking ? Thank you in advance.

[YuanLi_S_Intel]

Hi Jean, By right the I/O pin are tri-stated with weak pull-up before configuration, i dont see any problem here. If you would like to program the device again after it is in user mode, you may change the state of the unused pin. To do so, go to Quartus -> Device -> Unused Pin -> Input pin as tri-stated with weak pull up. YL

[JTixi]

​Hello!

I thank you for your reply. I think however that the JTAG chain is checked at beginning of normal programmation process, without tri-stating the I/O.  It is the raison why I allways get an error (Device not connected). Is there any method to force tri-state on I/O before programming or skip JTAG test, using a script on console for example ?

JMT.

[YuanLi_S_Intel]

Aplogize that TDO check cannot be disabled and all the JTAG pin (TDO) cannot be used as normal IO pin. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-v/max5_handbook.pdf (Page 43) Even if it is unused, you will need to leave it unconnected as per pin connection guidelines. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-v/pcg-01012.pdf Regards, YL