Is there a program to convert AHDL to VHDL?

[Altera_Forum]

I have an ancient EP1K design mostly in AHDL with one VHDL sub-module. Is there any way to automatically convert it to VHDL?

[Altera_Forum]

Believe it or not, I did search on the subject before posting this. Apparently not in the right forums. 

 After posting, the forum software found several potential answers. They pretty much boil down to:  1) rewrite it all yourself in VHDL 2) Use Xilinx's xport.exe to convert it.  I'm trying to avoid 1), and xport chokes because it expects ALL of the project hierarchy to be AHDL. I have one VHDL module in the project. So it errors.  I'm a little surprised that Altera hasn't written a converter. But maybe they are afraid people would use it and flee to other vendors.  So, if anyone has a good solution to this, please reply.  ~Ken

[Altera_Forum]

Im afraid the only options are the two you set out. If its that old a design, there cannot be too much code to convert. And also remember that AHDL is supported in all Quartus versions.

[Altera_Forum]

Actually there is no real need to convert AHDL in VHDL as Altera still supports AHDL. The only bottleneck is in simulating your designs but you can have the EDA writer put out a 'functional' netlist for 'RTL' simulation. Not ideal but it works. You can also appreciate that conversion AHDL into VHDL doesn't make the code any prettier or better maintainable, I guess. I haven't tried to convert AHDL to VHDL yet, but if you look at the Verilog to VHDL conversions Altera has done on some example designs you get an idea. 

Xilinx providing an 'xport.exe' of course is a way to lure Altera customers :( I suggest you stick with most of the AHDL code as it is, and convert the modules you have to work on by hand.

[Altera_Forum]

--- Quote Start ---  xport chokes because it expects ALL of the project hierarchy to be AHDL. I have one VHDL module in the project.   ~Ken  --- Quote End ---    Can you not learn enough AHDL to replace your 1 VHDL module with a 'dummy' AHDL module (just wire inputs to outputs or set all outputs to '0's)?  Run this through xport then replace your real VHDL module in the VHDL output?  Nial

[Altera_Forum]

It's simpler than that. xport doesn't really understand hierarchy. It just finds a new file with the sub-module's name and tries to convert it. The calling module converts correctly if its AHDL. So, just run the tool on the files you want and ignore the errors when it hits a VHDL submodule.