Issue with Nested Modules in ModelSim 20.1.1 - Not Following Verilog Rules

[aprilsohail]

Hi Intel Community,

I encountered an issue while testing ModelSim version 20.1.1  (Latest) related to Verilog syntax rules. I am sharing this here to bring it to Intel's attention.I tested the behavior of nested modules in Verilog to check if the tool adheres to Verilog language rules. According to Verilog standards, defining a module inside another module (module within module) is not allowed.

Observations:

1. ModelSim 20.1.1: The simulation runs successfully, producing an output. However, this behavior is incorrect as nested modules are not allowed in Verilog.
2. QuestaSim: When I ran the same code in QuestaSim, it correctly reported the error: "Module 'decoder' is not defined", which is the expected behavior.
3. EDA Playground: On EDA Playground, the simulation explicitly states: "Nested module is not allowed", aligning with Verilog standards.

Please investigate this issue in ModelSim 20.1.1. It seems the tool is not enforcing the Verilog rules for nested modules.

I understand Verilog rules well, and this test was purely conducted to evaluate how ModelSim enforces the language standards.Let me know if you need more details about the test case or if I can assist in further debugging.

Thanks

[ShengN_Intel]

Hi,

Possible to provide the test files? and I'll report this to internal engineering team

Thanks,

Regards,

Sheng

[aprilsohail]

sir use ModelSim 2020.1

[FvM]

Hi,
Modelsim has syntax level settings per source file. Syntax may be set to SystemVerilog despite of .v file type.

Apart from this point, Modelsim isn't a formal verification tool. I'm not sure if accepting certain language constructs beyond selected syntax level should be considered as bug. On the other side, you can't be sure that all Verilog or SV constructs are understood by a specific Quartus version, you need to check the language support specs.
Regards
Frank

[aprilsohail]

A basic verilog compiler should not allow nested modules, but here is not basic verilog compiler , it is from world's renowned company

[ShengN_Intel]

Hi,

I had tested in both Questa Intel 2024.1 and modelsim 2020.1, both can run the simulation.

Questa Intel 2024.1 screenshot:

modelsim 2020.1 screenshot:

I think can be run in simulator tool but not in synthesis tool.

Simulation tools are more permissive about the syntax and constructs used because they only need to simulate the design and do not need to map it onto actual hardware.

Synthesis tools map Verilog code onto physical hardware. They have stricter requirements.

Thanks,

Regards,

Sheng