Issue with lpm_divider

[Altera_Forum]

Hi, 

I am currently working on a block which calculates a configuration word to be sent to an external PLL chip based on a frequency that is sent from a higher application.   I am doing it in the schematic editor of Quartus using the megafunctions to implement the various subrtractions, divsions and multplications nessecery. When I simulate my circuit (attached) in modelsim, they output I obtain is incorrect. After debugging the circuit I have traced the issue to the output of the final stage (the output of central_freq_div_2). The inputs to these blocks are the expected values, but the division result is not as expected.    The numerator of the divider is 2 32 bit words (as I could not use a 64 bit constant) which has a value of x5A00000000000000, the denominator is a 40 bit value, 250,000,000 (xEE6B280) in my example. If I do this division in decimal, the answear comes out fine, but using the calculator in windows and doing the division in hexadecimal, the answear comes out incorrect (x60A302F9D), which curiously is also the result I see in modelsim.   I´m sure this issue has a simple explanation, but I´m a little lost. Is this an issue with modelsim, the lpm_divider megafunction or something else? Is there an issue when working with 64 bits (like in the windows calculator)? Can anyone see another way of getting around this issue?   I would be very grateful for any ideas. Many thanks

[Altera_Forum]

Hi, 

  --- Quote Start ---  The numerator of the divider is 2 32 bit words (as I could not use a 64 bit constant) which has a value of x5a00000000000000, the denominator is a 40 bit value, 250,000,000 (xee6b280) in my example. If I do this division in decimal, the answear comes out fine, but using the calculator in windows and doing the division in hexadecimal, the answear comes out incorrect (x60a302f9d)  --- Quote End ---    i think x60a302f9d is a correct result (not very very very carfully verified).  I see You work in unsigned :  signed give same result I think (in respect of size) but not fixed float, neither float IEEE... What "result" do you expect ? Are you tired ;-) ? Am I wrong ?  Another thing I notice :  Your design employes very "hungry" operations in term of logical ressources. No registers between operations, no pipeline make your design work in (very) low frequency. Do you aim to implement it in a FPGA (or CPLD) ?

[Altera_Forum]

Thanks for the reply. 

 Just realized the problem. I wanted to divide 11258999068426240000000 by 250000000 but when i convert the former to Hex in the windows calculator to verify the output it gives me 5A00000000000000 but the actual conversion turns out to be 2625A00000000000000. Using this value, I see that my design was fucntioning well all along. It seems I was asking too much of the windows calculator...pitty it took me so long to realize though...   Thanks again   PS.  As regards the point on timing, yes I´m aware of that, but at the moment I simply put togther this circuit quickly to verify the basic functionality.

[Altera_Forum]

Hi, 

 11 258 999 068 426 240 000 000 (approx 11.259e21) > 2^64 -1 ......2^64 appox 16e18 your 64 bit is too short.  Windows calc can handle 64 bit. It is Qword in hex.