Issues reading testvector file using Modelsim

[Altera_Forum]

Hello everyone! 

 I am trying to run a testvector from my code using SystemVerilog but I'm having an issue reading the file. My code is as follows:  logic testvectors; $readmemb("C:\Users\jbrookley\Desktop\EECS X497.2\Week 5\Q2\w5q2tv.tv",testvectors);  The error I am getting is:    --- Quote Start ---  # ** Warning: (vsim-7) Failed to open readmem file "C:UsersjbrookleyDesktopEECS X497.2Week 5Q2w5q2tv.tv" in read mode.# # No such file or directory. (errno = ENOENT) : C:/Users/jbrookley/Desktop/EECS X497.2/Week 5/Q2/W5Q2tb.sv(18)  --- Quote End ---    I know the file exists because I can copy and paste the location given and it will launch the file so that doesn't appear to be the issue. The code itself is more or less taken straight from a book (Digital Design and Architecture) so I wouldn't anticipate there being issues but clearly, something odd is going on (I had similar problems with previous code segments where my solution was to hard code the directory as I did here).   Has anyone seen this problem before? Any help would be greatly appreciated. Thanks!

[Altera_Forum]

You might try changing the \ to \\ or /. \ is an escape character in a Verilog string.

[Altera_Forum]

--- Quote Start ---  You might try changing the \ to \\ or /. \ is an escape character in a Verilog string.  --- Quote End ---    You nailed it right on the head! I changed the code from:  $readmemb("C:\Users\jbrookley\Desktop\EECS X497.2\Week 5\Q2\w5q2tv.tv",testvectors);  to:  $readmemb("C:/Users/jbrookley/Desktop/EECS X497.2/Week 5/Q2/w5q2tv.tv",testvectors);  Everything is working great now. Thanks!