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KSmil
Beginner
786 Views

JTAG Error when Acquiring Signals in Signal Tap (STP Suddenly Stopped )

 

I have been testing a number of iterations of the same build with the Arria 10 FPGA Development kit. At some point, between one build and another​, Signal Tap started showing freezing/crashing/showing the following error when trying to acquire samples.

 

 

 

Error 261002: Can't engage JAG communication. Select correct communications cable and device.

 

 

 

The sample clock I had been using was the output of a PLL which uses an off board clock source as it's input. This was sampling above 200MHz. I have also tried sampling using the automatically assigned Signal Tap clock, and a 50 MHz on board clock source. Each of these sources gives the same error.

 

 

 

I am able to program the board. Signal tap shows "Ready to Acquire". If I set a trigger and press 'play' to acquire, the software freezes as soon as the design starts receiving clocks.

 

 

 

In order to program the device again I have to turn it off and on (reset it) to be able to see the device from Signal Tap. However, it the JTAG chain can be seen from the Quartus Programmer.

 

 I have previously had trouble with the fitter in quartis assigning unused pins to locations that are used by the JTAG chain (particularly on the Max 10). I have assigned all the pins used in the design, none of which are used by the JTAG chain, max II, max Bid devices on the Arria 10 board. They are mostly assigned to FMCA port A, with a user LED, button and switch being used as well.

 

If anyone has seen any issues like this, or has any suggestions it would be much appreciated.

 

 

 

Thanks,

 

 

 

Karl

 

 

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2 Replies
ShafiqY_Intel
Employee
84 Views

Hi Karl,

 

Can you kindly try to change your TCK frequency to 6 MHz (default value)?

Kindly try it out with your design and let me know the result.

 

Thanks.😉😉😉

KSmil
Beginner
84 Views

Thanks for writing back to me.

 

I managed to fix the issue after a lot of digging. The issue was that I hat set a load of pins to be virtual pins (4 x 32 pins). However, these pins were bi-directional, and I hadn't realised that you can't set bi-directional pins as virtual. The only thing this did was to hide the pins from me in the pin planner. In Quartus, the fitter was assigning these pins to random pins on the FPGA.

 

The problem was that the fitter was randomly assigning some of these bi-directional pins from my design to FPGA pins designated by the JTAG chain. So after the FPGA was programmed, these pins were reassigned and the device couldn't be seen via the JTAG.

 

I solved this issue by assigning the bidirectional pins in the Pin Planner to pins that I knew would not be required by the design (FMC card, LCD screen, etc)

 

Thanks for you help though.

 

Karl 

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