L Tile/ H Tile Transceiver Native PHY Intel stratix 10 FPGA IP

[Pragya]

I see in the parameter list of this standard PCS- 8/10b encoding and decoding is enabled but the input/output to this block is 8b. Shouldn't it be 10b?

Also what is the difference between standard pcs with everything disabled but only with 8/10b endoder and decoder enabled and direct PCS?

[Ash_R_Intel]

Hi,

8b/10b encoder and decoder are enabled internal to the IP when selected. Tx side, user provides 8b data which is internally converted to a 10b data to transmit. Similarly, the Rx receives 10b data from serail interface and passes it through the decoder to provide 8b output to the user.

In PCS direct configuration the data flows through the PCS channel, but all the internal PCS blocks are bypassed.

Standard PCS still will have 8/10b encoder-decoder blocks in your case.

Regards