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LCD on Altera DE2 VHDL

Altera_Forum
Honored Contributor II
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Hello, 

I have a problem with written program VHDL to LCD on Altera DE2 with 2 lines. 

I have done on 7-seg and LED, and I want the same inscription on LCD witch is now and working on 7-seg. 

 

LCD is ready. Ports and pins are declared. 

 

LCD_POWERON: out STD_LOGIC; -- power on LCD_ENABLE: out STD_LOGIC; -- enable LCD_BL: out STD_LOGIC; -- back light LCD_RS: out STD_LOGIC; LCD_RW: out STD_LOGIC; LCD_DATA: inout STD_LOGIC_VECTOR (0 to 7)  

And this is fragment of code 

 

if (WL = '0') then -- button WL LEDY <= "000000000000"; LD7 <= "0111111"; LD6 <= "0111111"; LD5 <= "0111111"; LD4 <= "0111111"; LD3 <= "0111111"; LD2 <= "0111111"; LD1 <= "0111111"; LD0 <= "0111111"; licznik <= 0; zdarzenie <= 0; else if (falling_edge(CLK)) then if (zdarzenie = 0) then -- stop (2s) LEDY <= "000000000000"; LD7 <= "1000110"; LD6 <= "0100100"; LD5 <= "1111111"; LD4 <= "1111111"; LD3 <= "0010010"; LD2 <= "0000111"; LD1 <= "1000000"; LD0 <= "0001100"; licznik <= 0; zdarzenie <= 0; if (licznik <= TIME_2) then licznik <= licznik + 1; else licznik <= 0; zdarzenie <= 1; end if; elsif (zdarzenie = 1) then -- forward (4.5s) LEDY <= "000000000001"; LD7 <= "1000110"; LD6 <= "0100100"; LD5 <= "0100001"; LD4 <= "0100011"; LD3 <= "0001100"; LD2 <= "0101111"; LD1 <= "0100100"; LD0 <= "1111111"; if (licznik <= TIME_4_5) then licznik <= licznik + 1; else licznik <= 0; zdarzenie <= 2; end if; elsif (zdarzenie = 2) then -- right (1s) LEDY <= "000000100100"; LD7 <= "1000110"; LD6 <= "0100100"; LD5 <= "0100011"; LD4 <= "0000011"; LD3 <= "0001100"; LD2 <= "0101111"; LD1 <= "1111111"; LD0 <= "1111111"; if (licznik <= TIME_1) then licznik <= licznik + 1; else licznik <= 0; zdarzenie <= 3; end if; 

 

And I need the same inscription like on 7-seg, but now on LCD. 

Please help.
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