LUT for ADDER

[Altera_Forum]

Hello, 

 I make a code VHDL to create a 12 bits Adder. 12 bits adder consists of 12 1 bit Adder has 3 inputs and 2 outputs so we need 2 LUT each one 3 inputs to create 1 Bit Adder. so 24 LUTs for 12 bits adder. When i click on Analysis & Synthesis. Quartus II use automaticly the 4 inputs of each LUT and decrease the number of LUT from 24 to 15. my question is how i can oblige the quartus to creat the mappuing of LUT like i coded (24 LUT and use 3 input for each LUT) ? and other question : How i can implement a component in one LAB if i use the free licence of Quartus.  thank you NAOUSS

[Altera_Forum]

you mean you instained 12 full-adders . are you adding a constant signal? so the quartus turn on normal mode for le <- you out is optimized. 

try to turn on arithmetic mode fo le. you can do it from code if you add with non-constant driver, or can you use resource editor in techology map?