Large Multiplexer fitting problem

[Altera_Forum]

Hello, 

 I am implementing a reconfigurable architecture with a reconfigurable interconnection structure to be mapped into a stratix II fpga, the main problem i am having is when i try to fit the design into the FPGA because the interconnection structure has a large number of very large multiplexers (12-32bit 16 to 1 muxes). There is a way to reduce fitting time when implementing such a structure.  Thanks a lot!!!  juan

[Altera_Forum]

1 - Is the logic clocked? If so, can you pipeline the MUX into several stages? 

2 - You can use design partitioning to reduce your compile time. 3 - Faster machine. This can make a HUGE difference. I had one design that took 45 minutes on a single core machine and 12 minutes on a dual-core.  Jake

[Altera_Forum]

Designs that have lots of multiplexers can have fitting problems because they often have very high interconnect demand (per logic element). 

 One way you can tell whether this is the case for your design is to look for the Fitter info messages during routing that tell you what the interconnect demand is. They look like this:  Info: Average interconnect usage is X% of the available device resources  Info: Peak interconnect usage is Y% of the available device resources in the region that extends from location X??_Y?? to location X??_Y??  Typically, when X > 60% and/or Y > 90%, designs can have trouble routing (may need extra fit attempts, or may fail to route).  If you are using logiclock regions, it is important to try the design without them to make sure that your floorplan is not constraining the design in an un-natural way and causing higher interconnect demand.  Hope that helps.