Latency and Famx calcualtion

[Altera_Forum]

I am new to the tool and let me know if any mistakes in my process.  

 I need to know how fast my arithematic components can work in Startix2 devices.With these results, i can develop my control logic .    I am using parallel adder to implement in startix2 device using quartusII . I tried to setup required frequency is 380Mhz(2.625 ns). The TSU is within limits (1.9ns), where as TCO is 5.609ns. Does it mean, the Fmax for this ckt is 177mhz(1/5.609ns) or is there any other we can calculate the approximate frequency?.   How to find the latency of the circuit?. Since clock period is 2.625ns and the TCO is 5.609ns, Can i assume the output can be expected in 3rd clock cycle . Can i fix latency of the circuit is around 3 clock cycles. Is there any other way we can find the latency. I tried to simulate the gate level netlist with test bench, the output is showing randomly. It may be due to setup violations and metastability problems.   I will appreciate if you can help in understanding latency calculation.   Regards,  Sam

[Altera_Forum]

Hi Sam: 

 Based on your TCO timing, yes, I agree with th ~177 MHz fmax. However the limiting factor is probably not the cycle time, register to register, but the IO buffer. (TCO is Clock to Output)  So what this telling me, is you have a design that is trying to run the IO buffer at 350 Mhz, which is very difficult. (Not impossible, but very difficult depending on Board layout, and IO buffer selection)  FMAX is usually, how fast can you run, and get reliable data. Latency is how may clock cycles can does it take to propagate though the logic. (IE how many register delays)  Right now your TCO appears to be the limiting factor, so this can be improved by adding another register delay at the output, and making sure Quartus packs the output registers in the IO. Also selecting Faster IO standards helps.  Pete

[Altera_Forum]

In most cases, a simple TCO analysis won't be enough. The specific timing requirements of connected peripheral also have to be considered. In the present speed range, it's not unusual to have one or more separate PLL generated clocks to adjust the IO timing. After timing skews of FPGA, wiring and peripheral have been added, a positive window must remain.  

 So I doubt, if the maximum speed for a IO related application can be found without analyzing the respective peripherals timing. On the other hand, TCO shouldn't be the limiting factor then.

[Altera_Forum]

Thanks for your replies. My worry is how can i improve TCO value?. Any suggestion are welcome.  

 I need my design should work with 1 clock latency at 380mhz. I am unable to design not even adder at this frequency. I felt some setup problem in my flow. STARTIXII devices are about to work at 400mhz.   Please suggest if i need to set any timing parameters to meet my requirement.  --Sam