Launch to Latch Clock Timing (Slack Error)

Altera_Forum · ‎08-14-2012

I'm pretty new to TimeQuest Timing Analyzer and Constraining Nets, so any advice would be appreciated.

I have two clocks clk_50M (launch) and clk_125M (latch) that flags a slack error (-2.377). The data comes across the 50Mhz VME bus and clocked on the 125Mhz system clock to be used. Should I place a multicyle constraint on these nets?

--code sample

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--write to selected register if reg_write is high

if reset = '1' then

data <= "0000";

elsif clk_50 = '1' and clk_50' event then

data <= VME_data(3 downto 0);

end if;

Thanks!

Altera_Forum · ‎08-14-2012

The safest way is to use dc fifo to bridge data across.