Library Mapping File Help

[Altera_Forum]

Hi, 

 So basically, I want to force quatus synthesis tool to use only my own implementation of ANDs, ORs, MUXes, etc and only those and nothing else to synthesize the behavioural verilog files. I have already designed these in modelsim.   Can someone please help me out from here?   Thank you vik.vik

[Altera_Forum]

Can you elaborate? You can write structural code if you want, but there's no such thing as an AND, OR or MUX in the FPGA. It's all LUTs(and supporting logic like carry-chains), so unless you write LUTs, which I recommend against, then synthesis has to map to what's physically in the part. What might help is explaining why you want it to do this. My experience is writing low-level code is painful, slow, and provides very little benefit. I would only do it as a point solution.

[Altera_Forum]

first of all, thanks for the previous reply! 

 okay so here's what i want to do, but i guess i explained it poorly before.   so basically i am working on a new micro-architecture. what we have done is modified the functionality of basic gates such as AND, OR, etc to meet the requirements of what we want. Lets just call these gates shadow gates. to demonstrate that this idea works i built a simple arbiter using structural verilog. now i want to write an entire processor using that principle (using shadow gates).    so i intend to use behavioural verilog for writing this processor. however, when i synthsize, i need the quartus synthesizer to synthesize using only the shadow gates and muxes i have already built so that the entire processor is effectively using that new micro-architecture.   any ideas or thoughts?   Thanks again.. vik.vik

[Altera_Forum]

If you design and use and/or/nand/nor functions quartus is going to take that and convert it to logic that it uses. There's nothing you can do about that to my knowledge. Sure you can make your own AND() and OR() calls but in the end quartus is going to flatten that, run it through optimization routines and synthesize it to it's architecture. The only thing you might hope to get to retain some semblence to your original design is maybe some muxes.

[Altera_Forum]

thanks alt1000 for the reply... 

 the optimization stage will probably come after it has built the entire ckt using my shadow gates. so as long as the same functionality is retained i dont think it should make a difference?   I guess may be i am still not able to properly explain what i want to achieve?   if someone has any ideas, please go ahead and post them, in the mean while i will discuss this problem again with my peers in the lab and may be rephrase my question.   vik.vik

[Altera_Forum]

you can't replace how 

 a <= b & c;  will be synthesized. if you have some funky AND implementation, and want to use it, you will have instantiate your custom blocks directly, no behavioural logic.  --dalon

[Altera_Forum]

Hi vik.vik, 

 it is unclear what you actually try to achieve. Could you be more specific?     --- Quote Start ---  what we have done is modified the functionality of basic gates such as AND, OR, etc to meet the requirements of what we want. Lets just call these gates shadow gates. to demonstrate that this idea works i built a simple arbiter using structural verilog. now i want to write an entire processor using that principle (using shadow gates).  --- Quote End ---     What do you mean by "shadow gates"?   Are you intending to prototype some kind of asynchronous architecture based on handshaking protocols? Is it to avoid races and hazards that you specifically want to design up to the gate level? Do you need specific assumptions with respect to signal propagation delays?   More info would be welcome to be able to make some suggestions...