Logic gate output from bus

Altera_Forum · ‎01-03-2012

Hello to everybody,

I hope I am posting this at the right place.

My question is actually very simple. I have a bus, e.g. a[3..0]. And I want to make an OR gate with one output which makes ORs for all nodes in the bus, i.e. (a[3] OR a[2] OR a[1] OR a[0]).

In particular, I am looking for an symbol/component. I think there has to be a simple solution, but the primitive OR gate does not accept buses. The lpm_or gate would rather make an OR gate on two or more buses, but not on the nodes of one bus.

And since this question is also related, is there a function in AHDL or VHDL there for, for example OR(a[]).

Thank you in advance!

Altera_Forum · ‎01-03-2012

for a symbol, you may need to separate out each bit individually and input it into the gate. You can do this by named association

Forget about AHDL (its a dead language)

in VHDL, you can simply use one of the two methods:


library ieee;
use ieee.std_logic_1164.all; --library used everywhere
use ieee.std_logic_misc.all; --has some useful reduction operations
......
signal a : std_logic_vector(7 downto 0);
signal b : std_logic;
...
b <= or_reduce(a); --also, and, nand, nor, xor, xnor reduce functions

or when Altera finally add some decent VHDL 2008 support:

b <= or a;

Altera_Forum · ‎01-11-2012

Yeah, thanks. In the last time I studied a bit VHDL and that's exactly I was looking for.