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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Loop unrolling doesn't improve the processing time of radix-4 butterfly

JBorr6
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I am running an emulation of an FFT using aocl 19.1.0.240 with s10_gh1e1_4Dx2 board.

 

But when I tried comparing the radix-4 butterfly with (#pragma unroll before the for loop) and without loop unrolling, there is no difference in their processing time. Can anyone help me with this? Thank you so much.

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