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Hi,
I am currently encountering numerous errors during the compilation of my design in Quartus Prime Lite (version 19.1.0). According to the user guide, the device part I am using supports 1.8V LVCMOS. Could you please provide guidance on how to resolve these compilation issues?
I have attached the screen shot of the errors.
Thank you
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I wonder how you assigned the shown I/O standards. There's no 3.3V LVDS standard available for any FPGA. Similarly, the MAX10 1.8V I/O standard has a different name. Suggest to select I/O standard either in pin planner or assignment editor out of available settings.
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Hello,
Can you confirm how you assigned the I/O standard?
Regards,
Aqid
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Hi,
Earlier I used the syntax
"set_instance_assignment -name IO_STANDARD "1.8-V LVCMOS" -to FLASH_1_DQ0"
Later , I changed it to
"set_instance_assignment -name IO_STANDARD "1.8-V" -to FLASH_1_DQ0".
Instead of "1.8-V LVCMOS" I only specified "1.8-V" and it worked.
Thank you
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I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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