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Macros with arguments in Verilog/SystemVerilog

Altera_Forum
Honored Contributor II
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Hi all, 

 

I want to used parameterized Verilog macros in my code. 

It looks somewhat as shown below: 

 

`define ACTIVE_EDGE posedge parameter ISO_SENSE=1; always @(`ACTIVE_EDGE isolation_ctrl) if(isolation_ctrl==ISO_SENSE) power_iso_flag=0;  

 

I used "tick define" macro and parameter as I need my code to be somewhat generic. 

 

Now, I want to extend the same for the following case: 

(1) isolation_ctrl can be a vector with width N and it will have corresponding ISO_SENSE values. That is, 

 

logic [NO-1:0] isolation_ctrl; 

bit [NO-1:0] ISO_SENCE; 

(2) If ISO_SENCE is 1, the macro `active_edge should take value posedge. whereas, it should take negedge for iso_sence=0. 

 

I tried to do so using generate and macro with argument as follows: 

 

`define str1 posedge `define str2 negedge `define ACTIVE_ISO_EDGE(a) ( a ? `str1 : `str2 ) ... module abc ( ...); ... ... bit sences='{1, 0, 0, 1}; ... ... generate genvar j; for(i=0; i<NO_OF_DOMAINS; i++) begin always @( `ACTIVE_ISO_EDGE( sences) isolation_ctrl ) if(isolation_ctrl==ISO_SENSE) power_iso_flag=0; end endgenerate ... ... endmodule 

 

However, it gives the following error: 

 

error-[se] syntax error  

following verilog source has syntax error :  

"env/assertions.sv", 309 (expanding macro): token is 'posedge'  

always @(`active_iso_edge(ds[j]) isolation_ctrl_for_all_domains[j]) 

__________________________________^ 

 

Can anyone please help me solve this? I am not getting the exact way in which I can employ macros to make everything generic along with generate. 

Hoping for some useful comments. :) 

 

 

Thanks, 

Gaurang
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Altera_Forum
Honored Contributor II
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It appears you have too many "`" in the expression. In your first example, ACTIVE_EDGE expands to posedge, but in the second example ACTIVE_ISO_EDGE( sences[i]) expands to `posedge, so the result will be ``posedge.

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