Managing input on the FPGA board

[Altera_Forum]

Hello, 

I have following kind of input in my VHDL Program:  type binary_array is array(0 to 1099) of std_LOGIC_VECTOR(13 downto 0);  I run the Program successfully in Quratus and also tested it by giving such 1100 input via Testbench in Modelsim.  But I am wondering how can I run that program on real FPGA board because number of input in real case is several thousands (not equal to 1099) which is not even fixed as input is given by means of antenna, receiver, Analog to digital converter, etc??  can anybody give some idea how can I manage the input?  --Thanks in advance

[Altera_Forum]

My suggestion would be to consider using the in system memory content tool. You could add a VHDL/Verilog module to wrap around a RAM, and using this RAM to be your stimulus/response. -James

[Altera_Forum]

--- Quote Start ---  Hello,  But I am wondering how can I run that program on real FPGA board because number of input in real case is several thousands (not equal to 1099) which is not even fixed as input is given by means of antenna, receiver, Analog to digital converter, etc??   --- Quote End ---    If your signal is from ADC then you process it as it comes. If you have to store it at some point then you can use memory defining how much storage is required. fpga pins are kept for ADC inputs. You don't have to compare an internal simulation stimulus with ADC in this way.

[Altera_Forum]

Hello, thanks for the reply first. 

  --- Quote Start ---  If your signal is from ADC then you process it as it comes.  --- Quote End ---    Yes, My signal is from ADC (daughter card: http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&no=278) to FPGA pins.   Does it mean that it repeat/reset automatically as soon as number of input reaches to maximum defined limit in the program (e.g. in my case 1099)?  and it works even the input is more than 1099 samples?    --- Quote Start ---  If you have to store it at some point then you can use memory defining how much storage is required.  --- Quote End ---    Could you please provide a short description/example for this?

[Altera_Forum]

I take it you got some program inside your fpga that interfaces with your 0:1099 vector generator. Now you are happy with your program and want instead to get data from ADC then you connect 14 bits from ADC to your module instead of your vector generator. If ADC is not 14 bits then you resize it. 

 That is assuming your program is meant to process ADC data directly. ADCs are various and you may need to do some reformatting if it is not giving you the right data format.  Regarding start/reset then it is up to the way you are processing. If you are processing a continuous stream sample by sample then you don't need to think the same way as the case of block processing when you process a defined frame from start to end in which case you will need to store a frame while processing another.   I can't give helpful examples without knowing what you want to do to inputs. It could be you want first to filter the data in a LPF then you do that nonstop. It could be then you do fft then you process it frame by frame and so on.

[Altera_Forum]

--- Quote Start ---  I take it you got some program inside your fpga that interfaces with your 0:1099 vector generator. Now you are happy with your program and want instead to get data from ADC then you connect 14 bits from ADC to your module instead of your vector generator. If ADC is not 14 bits then you resize it.  --- Quote End ---   Yes, exactly. ADC is also 14 bits    --- Quote Start ---  That is assuming your program is meant to process ADC data directly. ADCs are various and you may need to do some reformatting if it is not giving you the right data format.  --- Quote End ---   The Daughter card uses ADC (AD 9248) whose output is either 2's complement or offset binary based on data format select pin (DFS) selected, as mentioned in its data Sheet. but I am still not sure which one is in my case as DFS selection is not clear to me from data sheet for channel A. It seems to me it is 2's complement output in channel A of ADC which I am using in my case.    --- Quote Start ---  Regarding start/reset then it is up to the way you are processing.  --- Quote End ---   I have to detect certain patterns of 5 pulses(every pulse have close to 25 samples) from the continuous streams of input coming from ADC and as soon as this pattern is detected I have to store the input data starting from that detected point. I have also attached the simulation here for clarification. Note: in this simulation, only 512 input is considered instead of 1099 I mentioned above.

[Altera_Forum]

--- Quote Start ---  Yes, exactly. ADC is also 14 bits I have to detect certain patterns of 5 pulses(every pulse have close to 25 samples) from the continuous streams of input coming from ADC and as soon as this pattern is detected I have to store the input data starting from that detected point. I have also attached the simulation here for clarification. Note: in this simulation, only 512 input is considered instead of 1099 I mentioned above.  --- Quote End ---    Once you detect the pattern then you save input data?? for how long and what to do with it? It is the subsequent processing that determines why and how much you save.

[Altera_Forum]

--- Quote Start ---  Once you detect the pattern then you save input data??  --- Quote End ---   YES    --- Quote Start ---   for how long and what to do with it?  --- Quote End ---   save 6400 samples of such inputs as soon as that pattern is detected. and extract that saved data to computer if there is anyway.  This task should be done every time continuously, I mean every time detect pattern from uninterruptibly incoming signal from ADC and as soon as that pattern is detected extract 6400 sample to the computer.   Thats why I am confused about which size should I choose as input(of 14 bit) in VHDL program.

[Altera_Forum]

Your frame is 6400 samples each 14 bits. That needs 89600 bits (87.5K). You can do that in many FPGAs and it suits large rams. You may need to use either two such rams or one fifo. 

 Two rams in case one may overflow/underflow so one reads ADC while the other is read to PC then swap the order. Your main task is to do the swap logic.  Or use fifo controlling rate so that PC catches up in time. Your main task here is to match the read/write speeds.

[Altera_Forum]

--- Quote Start ---  Your frame is 6400 samples each 14 bits. That needs 89600 bits (87.5K). You can do that in many FPGAs and it suits large rams. You may need to use either two such rams or one fifo.  --- Quote End ---   I am using Cyclone IVE FPGA which has 2 MB SRAM. I am planning to use this SRAM in following way (with right pin assignment for SRAM) for this purpose::  library ieee; use ieee.std_logic_1164.all;  entity single_port_ram is  port  (  data : in std_logic_vector(13 downto 0);  addr : in natural range 0 to 6399;  we : in std_logic := '1';  clk : in std_logic;  q : out std_logic_vector(13 downto 0)  );   end entity;  architecture rtl of single_port_ram is   type memory_t is array(0 to 6399) of std_logic_vector(13 downto 0);     signal ram : memory_t;     signal addr_reg : natural range 0 to 6399;  begin   process(clk)  begin  if(rising_edge(clk)) then  if(we = '1') then  ram(addr) <= data;  end if;     addr_reg <= addr;  end if;    end process;    q <= ram(addr_reg);   end rtl;  Does it work for this purpose or not??   One more thing, how can I extract/access these 6400 samples of data on PC every time may be in some text file format?

[Altera_Forum]

you have to access the memory via the same address and Q ports you have put into the code. but remember rams can be dual ported, so you can add another address port to read to the PC. But not as a text file (unless you write some software to read the data and write it to a text file)

[Altera_Forum]

--- Quote Start ---  remember rams can be dual ported, so you can add another address port to read to the PC.  --- Quote End ---   Sorry, I didn't understand it.  Info of SRAM I am using:  2MB (1Mx16) SRAM SRAM_ADDR[19..0] i.e. 20 bit address port SRAM_DQ[15..0] i.e. 16 bit data port  using Dual ported here means assign half of the address port to read to the PC and rest half for input of memory ?? or anything else?  and what is the meaning of read to PC? I mean by which interface to PC and in which format?

[Altera_Forum]

all the internal memory on the FPGA is dual ported. So the same memory hass access from two sepearte things. So there are 2x 20bit address port and 2x 16 bit data port (in the configuration you're talkingabout). 

 I suggest reading the altera cyclone guide (specifically the ram architecture) and the quartus HDL coding styles guide.

[Altera_Forum]

--- Quote Start ---  I suggest reading the altera cyclone guide (specifically the ram architecture)  --- Quote End ---   I found one here: http://www.altera.com/support/examples/vhdl/vhd-true-dual-port-ram-sclk.html  Is it the right one what you have suggested?

[Altera_Forum]

That might help, but I was refering to the alter coding guidelines: 

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf  and the cyclone4 handbook, chapter on memory elements: http://www.altera.com/literature/hb/cyclone-iv/cyiv-51003.pdf