Max number of outputs from a PLL

[Altera_Forum]

What are the maximum number of clock outputs from a PLL. I think there are there is max option of 9 in the GUI. But from the verilog code of the PLL it seems that 18 clock outputs are possible from the PLL.parameter output_clock_frequency0 = "0 ps", parameter phase_shift0 = "0 ps", parameter duty_cycle0 = 50, parameter output_clock_frequency1 = "0 ps", parameter phase_shift1 = "0 ps", parameter duty_cycle1 = 50, parameter output_clock_frequency2 = "0 ps", parameter phase_shift2 = "0 ps", parameter duty_cycle2 = 50, parameter output_clock_frequency3 = "0 ps", parameter phase_shift3 = "0 ps", parameter duty_cycle3 = 50, parameter output_clock_frequency4 = "0 ps", parameter phase_shift4 = "0 ps", parameter duty_cycle4 = 50, parameter output_clock_frequency5 = "0 ps", parameter phase_shift5 = "0 ps", parameter duty_cycle5 = 50, parameter output_clock_frequency6 = "0 ps", parameter phase_shift6 = "0 ps", parameter duty_cycle6 = 50, parameter output_clock_frequency7 = "0 ps", parameter phase_shift7 = "0 ps", parameter duty_cycle7 = 50, parameter output_clock_frequency8 = "0 ps", parameter phase_shift8 = "0 ps", parameter duty_cycle8 = 50, parameter output_clock_frequency9 = "0 ps", parameter phase_shift9 = "0 ps", parameter duty_cycle9 = 50, parameter output_clock_frequency10 = "0 ps", parameter phase_shift10 = "0 ps", parameter duty_cycle10 = 50, parameter output_clock_frequency11 = "0 ps", parameter phase_shift11 = "0 ps", parameter duty_cycle11 = 50, parameter output_clock_frequency12 = "0 ps", parameter phase_shift12 = "0 ps", parameter duty_cycle12 = 50, parameter output_clock_frequency13 = "0 ps", parameter phase_shift13 = "0 ps", parameter duty_cycle13 = 50, parameter output_clock_frequency14 = "0 ps", parameter phase_shift14 = "0 ps", parameter duty_cycle14 = 50, parameter output_clock_frequency15 = "0 ps", parameter phase_shift15 = "0 ps", parameter duty_cycle15 = 50, parameter output_clock_frequency16 = "0 ps", parameter phase_shift16 = "0 ps", parameter duty_cycle16 = 50, parameter output_clock_frequency17 = "0 ps", parameter phase_shift17 = "0 ps", parameter duty_cycle17 = 50,

[Altera_Forum]

It depends on the specific device. 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altpll.pdf Table 6 might help.