Message Waiting for clock in Signal tap for input external clock

[DmitryKo]

Hi, all
I am using Quartus Prime Standard Edition version 16.1.2 Build 203
Device Cyclone V 5CEBA8F23C8

Approximately in more than 50 % of compilations of my project I got message Waiting for clock in Signal Tap. When the project was smallest I didn't see the message, but with growth the project size this message became blocking. 
I am working in the company where are some FPGA developers who using Quartus during 10 years and more, but nobody from them can't understand the reason of the this kind of behavior. 

I tried a lot of variations of settings but situation with this message is stable. Help me please to understand the reason of this message.
When i got compilation with Waiting for clock message this compilation do not work properly. This I see by behavior the device connected to outputs of FPGA, on which I generate signals with my logic. When compilation produces build without Waiting for clock message the connected device is working properly. But this situation occurs less and less often.
To get compilation without Waiting for clock message I use different tricks. For example, switch off 2 of 4 channels in my project and add big Signal Tap instance. My project includes 4 identical by logic control channels. But my tricks do not always lead to results.

I using one or more Signal Tap instances in the compilation and see the trend that message Waiting for clock arises more often when I add one big or two Signal Tap instances into compilation.   

Most interesting case is when I compile the project with one simplest Signal Tap instance, in which clock for Signal Tap is external clock 25 MHz on the input pin of FPGA (pin E10, 3,3V LVCMOS). The signal from this pin is connected to refclk of PLL (altera_pll, integer N mode, 25MHz to 150 MHz output clock). locked signal of this PLL is the only one signal in Signal Tap instance. And this compilation show Waiting for clock message in Signal Tap.

Please help me understand the reason and fix this blocking error or bug. Thank you very much in advance

Dmitry

[FvM]

How about design timing analysis results?

[DmitryKo]

Hi

As a result of optimization, I increased the Fmax to 138 MHz

[sstrell]

Why don't you use an output clock of the PLL for your capture clock instead of the input reference clock?  The output clock is what is used to clock your logic anyway (I presume) so that should be the clock you use for Signal Tap.

[DmitryKo]

Hi,

In main project I used output clock to clock all my logic and clock Signal Tap instance. But got problem with Waiting for clock and started to investigate. When I replaced clock for Signal Tap instance from PLL output clock to input clock the problem with Waiting for clock message still exists.

[sstrell]

I'd check your clock source.  I've never seen "Waiting for clock" with a dev kit, so if this is a custom board, I'd check your source clock from the board.

[DmitryKo]

This is custom board.
I found the reason and solution.
Clock from external board is routed to 4 input pins of FPGA, but used in the FPGA only one from them. 
The solution: define rest pins as inputs in Pin Planner. Input pins were connected to external signal but not defined in Pin Planner.
Thank you to all. 

[TingJiangT_Intel]

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