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I'm designing circuits on a Cyclone 2 Development Board in Quartus II 9.0 SP2 via block scematics. Recently, I observed a mismatch between my pin planner assignments and the LED-display on the development board. Means, although not assinged at all (as double checked in the Pin Planner), one LED (LEDR0-LEDR9) switches on when circuit is running. LEDs which are supposed to turn on remain being off but different LEDs turn on instead. This is reproduciable.
Does anybody has an idea what the reason might be for this strange behavior?Link Copied
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Review the *.pin file for the actual assignments. When you say "pins have not be assigned at all", they may be nevertheless used by Quartus or take a default state.
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Thanks for the quick response.
In fact there is an assignment to a databus noted in the .pin file. The pin planner does not list this assignment. How can I get rid of this assignment?- Mark as New
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It's normal operation.
If there are no pin assignments for the databus, it's most likely present in the design's top entity port and assigned by Quartus automatically. You have to comment the respective port entries to prevent Quartus from assigning pins to them. If the signals are accessed in the design, you can also declare them as virtual.- Mark as New
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Alright, I have to ask some basic questions now.
--- Quote Start --- You have to comment the respective port entries to prevent Quartus from assigning pins to them. --- Quote End --- Where can I do this (and how)? I was looking for a place I can do this but no success yet. --- Quote Start --- If the signals are accessed in the design, you can also declare them as virtual. --- Quote End --- I tried to delcare the databus pins as virtual in the assignment editor but it was unsuccessful. Although one LED stopped turning on whilst operation others keep turning on (I doubt my declaration had any effect on the malfunction since the assignment entry kept unchange in the .pin file). So here again, where can I change the parameter of the assignment (and how)? Thank you- Mark as New
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I see, that you implemented the design in schematic entry. In this case, the unwanted output and bidir pins should be removed from the top schematic. I don't know, if and how virtual pins can be defined in schematic entry.

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