I've also posted this here (first time poster)
I've demonstrated Ethernet capabilities by following this tutorial, where it generated a .elf file in /server/master_image/server.elf. I was then able to access my FPGA through telnet.
I've imported a different project, which compiled and built without errors, but does not generate the .elf file in the /project/master_image/ directory. There are however both top.pof and top.sof files.
Thanks in advance.