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Altera_Forum
Honored Contributor I
949 Views

Mod5 Counter

I need to do a VHDL program and I need to replace the use of 74191 IC and with the aid of the the FPGA I need use the toogle switches to start the count in mod5. Till now this is the program that I've done can someone guide me what should I do next and another question how do I need to connect the pin from the pin planner. 

 

library ieee; 

use ieee.std_logic_1164.all; 

 

 

 

 

entity assignment is  

port( 

Clock: IN STD_LOGIC;  

count : BUFFER STD_LOGIC_VECTOR (3 DOWNTO 0):= x"0000"; 

I : IN STD_LOGIC_VECTOR (3 DOWNTO 0);  

o : BUFFER STD_LOGIC_VECTOR (7 DOWNTO 0) := x"0"  

 

);end ENTITY; 

 

 

architecture BEH of assignment is -- 

 

 

begin 

process (I) --process is sensitive to A and B 

variable clk_cnt : integer range 0 to 50000000 :=0;  

variable x : integer range 0 to 8 :=0; 

 

begin  

 

 

 

if (clock'event and clock = '1') then 

clk_cnt := clk_cnt + 1; 

 

 

if (clk_cnt = 49999999) then 

x:= x + 1; 

end if; 

end if; 

 

if (x = 2) then 

O<= "11011010"; 

end if; 

 

if (x = 3) then 

O<= "11110010"; 

end if; 

 

if (x=4) then 

O<= "01100110"; 

end if; 

 

if (x=5) then 

O<= "10110110"; 

end if; 

 

if (x=6) then 

O<= "10111110"; 

end if; 

 

if (x=8) then 

x:=2; 

end if; 

 

end process; 

 

 

end ARCHITECTURE;
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1 Reply
Altera_Forum
Honored Contributor I
102 Views

please use code tags and indentations for easier reading, as for the pin planner search the forum, there are posts that might help you, if you still have problems, please start a separate thread for that. 

 

As you talk about VHDL program, I assume you are new to fpga's. So a few tips: 

Try using signals instead of variables, this will help you with debugging and will make the behavior more predicitve. 

vhdl has an elseif statement: if condition then dosometing elsif condition dosomethingelse else doanotherthingelse end if; 

as for your counter I do not quite understand what you want. 

Apart from that, try thinking of the hardware you want to create.  

 

(and try to avoid using buffers instead of in, out,inout, as far as I know this is considered bad practise, use a internak signal instead.)
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