ModelSim-Altera exiting

[Altera_Forum]

Hi all. I am trying to go through the tutorial (oem_tutor.pdf from Help>PDF files>Tutorial). When I get to the step : Loading the design into the simulator (on page T22), the simulator starts to do some things and then just exits. No warning or anything - it just closes. 

 What am I doing wrong?  I have version 6.1g  Kevin  btw, am I right in I read that Quartus can't nativly simulate VHDL??? Which means I must use ModelSim?

[Altera_Forum]

--- Quote Start ---  am I right in I read that Quartus can't nativly simulate VHDL??? Which means I must use ModelSim?  --- Quote End ---    The Quartus native simulator handles VHDL and Verilog source files just fine. It just doesn't support test benches. If you are using a test bench, you need a simulator like ModelSim.

[Altera_Forum]

I would much rather use the internal simulator. 

 I have v8.0 of the web edition. When I click on the button to specify a Simulator input file, no files show up in the dialog. Although it says it compiled with no errors (but with 4 warnings). The output files go into the project directory, right?  If you can't tell, I am new to this. I am used to uC's.  Thanks, Kevin

[Altera_Forum]

--- Quote Start ---  When I click on the button to specify a Simulator input file, no files show up in the dialog.  --- Quote End ---    The simulation input files are the stimulus files such as a vector waveform file. This is what the Quartus native simulator uses instead of a test bench.  For functional simulation, the source files are used when you run "Processing --> Generate Functional Simulation Netlist". For timing simulation, the source files are used for the compilation; the simulation uses a postcompilation netlist.

[Altera_Forum]

Ahhh. So, I have to make a stimulus file. I will give it a try. 

 Thanks!  Kevin