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I am a new student using a Quartus II 10.0 sp1 and ModelSim Altera Starter edition 10.1d. I am attempting to reproduce a lab project I did at school and upon finishing a simple 5 gate logic diagram schematic I go to processing>start compilation. Everything moves forward without problems until the ModelSim software opens. A message appears at the bottom of the ModelSim screen saying "--Compiling architecture structure of file" then nothing happens. In the task panel on the Quartus II screen progress just hangs at 83%.
Any ideas what I'm doing wrong? At school this worked just fine except I don't remember ModelSim being part of the process. Truth be known, I'm not even sure why it is necessary to compile a block diagram file. This is really sort of confusing.Link Copied
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Model Sim doesn't support schematic files ( bdf ). You have to convert it to vhdl to simulate the circuit. Did you write the testbench?
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Of course you're right. The problem is that in our lab we use version 9.0 sp1 and I downloaded the wrong version. I tried to search for similar problems but I'm so new that I didn't ask the right questions, otherwise I'd have seen that this issue was addressed many many times in the past. Sorry about that. ;-)
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Did you compile the testbench from Quartus or did you make a project on Model Sim?
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In our class we're not using ModelSim, but sticking with the old-school vwf. files. My understanding is that ModelSim is way better, but for my purposes I had to uninstall the version of Quartus II I was using and install the old 9.0 sp1 version.
Thanks again for answering my question so quickly.
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