ModelSim Error Undefined variable

Altera_Forum · ‎12-22-2011

Hello,

While i was reading ModelSim Altera tutorial i created module modelSimTut in quartus 11 on verilog. It compiled fine. Then i opened ModelSim and created a project. In directory work i have created test.v with such code

module test;
  
reg clock, enable, load;
initial 
begin
  clock = 1'b0;
  forever# 5 clock =~clock;
end
always @ (posedge clock)
begin
 modelSimTut mod1 (.start(enable), 
              .clock(clock), 
              .load(load));
end
endmodule

but when i try to compile, there is an error near modelSimTut mod1 (Undefined variable: modelSimTut). I tried to add modelSimTut.v to project, to copy it to the same with test.v folder. I also tried to add its directory to source directories for ModelSim, but i still can`t compile it becouse an error.

Also interesting that modelSimTut is highlited by blue and if open describe there is a path to modelSimTut.v file.

Help me please to understand the reason of this problem.

Altera_Forum · ‎12-22-2011

Modelsim needs to be used to compile both source files, eg.

1) Create a work library

vlib work

vmap work [pwd]

2) Compile your source, eg., use the following form for each of your source files;

vcom vhdl_file.vhd

vlog verilog_file.v

vlog -sv systemverilog_file.sv

3) Compile your testbench

vlog verilog_tb.v

4) Run the testbench

vsim -t ps -novopt verilog_tb

add wave *

run -a

The GUI will have a similar procedure. Personally I use the command line.

Cheers,

Dave

Altera_Forum · ‎12-23-2011

Thanq very much for your relpy.

When i tried to do this throug script i found that ModelSim can`t open modul because a white space in the path to its file.

Altera_Forum · ‎12-23-2011

The error message is primarly caused by a Verilog syntax error. Your trying to instantiate a module inside a sequential block, which isn't possible.

Altera_Forum · ‎12-23-2011

Thanks a lot, gentleman.

it is beautifull that there is one place where you can ask questions without fear of looking foolish and more about to get an answer)