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ModelSim Error: (vsim-3009) [TSCALE]

Altera_Forum
Honored Contributor II
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I downloaded and installed the ModelSim tools (Altera Starter Edition 10.0d) from the Altera website. Attempting to get thru the tutorial (Under Help in ModelSim), I get this error when I try to load test_counter (as directed on page 16 of the tutorial): 

 

ModelSim> vsim work.test_counter# vsim work.test_counter # Loading work.test_counter# Loading work.counter# ** Error: (vsim-3009) [TSCALE] - Module 'test_counter' does not have a timeunit/timeprecision specification in effect, but other modules do.# Region: /test_counter/dut# Error loading design 

 

Can someone please help me resolve this? Thanks. It's difficult when the tutorials don't work.  

 

Doug 

 

.
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Altera_Forum
Honored Contributor II
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Add this to the top of the file that Modelsim is complaining about: 

 

// Modelsim-ASE requires a timescale directive `timescale 1 ns / 1 ns  

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
9,808 Views

 

--- Quote Start ---  

Add this to the top of the file that Modelsim is complaining about: 

 

// Modelsim-ASE requires a timescale directive `timescale 1 ns / 1 ns  

--- Quote End ---  

 

 

Thanks, Dave. I appreciate it. 

 

Doug 

 

.
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Altera_Forum
Honored Contributor II
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You can always try typing  

 

verror 3009 

 

 

to see if there is more information about the error you are getting. In this case, it produces 

 

$ verror 3009 

 

vsim Message# 3009: 

A module without a `timescale directive in effect, and without 

explicit timeunit and timeprecision declarations, uses the 

simulator resolution limit for both its time unit and time 

precision. This may result in incorrect delays and unintentional 

behavior in the module. Beware of simulator performance impact, 

and consider using the vlog -timescale or vopt -timescale options 

as a workaround. This message can be downgraded to a warning with 

-warning 3009, suppressed with -suppress 3009, or suppressed 

with +nowarnTSCALE. 

[DOC: QuestaSim User's Manual - Verilog Simulation Chapter]
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