[ModelSim] Maximum of 32bit vector wave is supported

[Altera_Forum]

I am trying to simulate a vhdl design i've made which takes in a 48bit key as an input however when I try and simulate this with modelsim-altera I am getting an error saying that maximum of 32bit vector wave is supported. How can I get around this problem? Is it because the free versions only support 32bit input vectors? 

 The line of code in my VHDL entity looks like:  K : IN STD_LOGIC_VECTOR(47 DOWNTO 0);  And the exact error looks like:  Maximum of 32bit vector wave is supported 

[Altera_Forum]

I've used Modelsim with 256-bit signals without any problem, even with the Altera edition. Are you sure this error message refers to that exact line in your code, and not somewhere else? There could be restrictions in what Modelsim can display, rather than simulate.

[Altera_Forum]

With the waveform editor it seems that it isn't implemented I have been told this by an Applications Engineer at Altera.