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Altera_Forum
Honored Contributor I
5,491 Views

ModelSim: Warning: NUMERIC_STD."=": metavalue detected, returning FALSE

Hi, 

 

I'm having trouble with a testbench I wrote. When I include a particular 'if' statement, the design compiles/synths, then I run the functional simulation in modelsim, and get: 

 

Warning: NUMERIC_STD."=": metavalue detected, returning FALSE 

 

Naturally, I assumed this was due to failing to initialize, so I went back to my testbench and initialized all inputs to '0'. The thing is, the metavalue warning leads back to the FFT altera IP I'm using, and is several layers deep. Also, my if statement is a comparison to a STD_LOGIC type signal, and the warning mentions NUMERIC_STD. My signal is initialised to 0, but is set to 1 due to being mapped to the output of a lower level module.  

 

I've uploaded the offending process here (the if statement that causes the warning is on line 5, and the end if etc. is commented out): https://pastebin.com/sztwatgn 

 

If I remove the if statement, my design compiles and is able to simulate. If I leave the if statement in, when I run a simulation, nothing happens and I get repeat warnings at 0ps for this error.  

 

The ModelSim warnings are here:  

# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0# Time: 0 ps Iteration: 0 Instance: /top_tb/uut/fft_inst/fft_ii_0/apn_fftfpbdr_top_inst/source_control_inst# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE# Time: 0 ps Iteration: 0 Instance: /top_tb/uut/fft_inst/fft_ii_0/apn_fftfpbdr_top_inst/sink_ctrl_inst
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2 Replies
Altera_Forum
Honored Contributor I
2,157 Views

Yes, this will likely be signals inside the design being uninitialised, and fairly normal. So normal and annoying, there is an option to turn warnings like these from numeric_std off. 

Simulation -> runtime options -> "suppress warnings" from Synopsys Packages (from std_logic_unsigned/arith) From IEEE packages (numeric_std) 

 

If you're running from a script, set these variables before the run command: 

 

set StdArithNoWarnings 1 set NumericStdNoWarnings 1
Altera_Forum
Honored Contributor I
2,157 Views

 

--- Quote Start ---  

Yes, this will likely be signals inside the design being uninitialised, and fairly normal. So normal and annoying, there is an option to turn warnings like these from numeric_std off. 

Simulation -> runtime options -> "suppress warnings" from Synopsys Packages (from std_logic_unsigned/arith) From IEEE packages (numeric_std) 

 

If you're running from a script, set these variables before the run command: 

 

set StdArithNoWarnings 1 set NumericStdNoWarnings 1  

--- Quote End ---  

 

 

Thanks for the help. It was not the warnings that bothered me but that I assumed they were stopping my waveform from generating. Actually it was something unrelated - in the code I pasted, there is a possibility for no time to run at all, as there's no wait statement. Moving onto the next state was dependent on x cycles occurring, so this broke the entire simulation and I assumed it was the warnings. Fixed now - thanks for telling me about the warnings commands.
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