ModelSim fails to recognise internal component connections

[Altera_Forum]

I am trying to simulate in Modelsim (altera or xilinx web edition) a verilog only project consisting of top level and few components. 

All components have wire type outputs. The problem is that Modelsim doesn't recognise the drive of any component's output connected to another's input. Yet it accepts the drive when connected to an output of toplevel itself. What am I missing? Is there anything else to do about binding? Any help appreciated. This problem does not occur with vhdl projects.

[Altera_Forum]

Maybe it would be helpful to clarify the problem that you experience by a small sample Verilog description.

[Altera_Forum]

Thanks sanmao, 

 I just rewrote these three attached modules which shows the behaviour.   one module should write to the other which will then produce final data.   If I connect final data out of toplevel then data is ok. If I keep it internal all is dead.   However, the internal connection across the two modules fails to drive.   Regards

[Altera_Forum]

--- Quote Start ---  Thanks sanmao,   I just rewrote these three attached modules which shows the behaviour.   one module should write to the other which will then produce final data.   If I connect final data out of toplevel then data is ok. If I keep it internal all is dead.   However, the internal connection across the two modules fails to drive.   Regards  --- Quote End ---    Hi kaz,    maybe I wrong, but I would say your simulation is running forever. There is no condition for stopping the simulation like "$finish". I would add this :  //generate reset initial begin  reset = 1'b1;  reset =# 1000 1'b0;  #1000;  $finish; end  You can define the length of the simulation with the value above "$finish".  I don't know modelsim, but for other simulators you need to add something like this in case you want to use a waveform viever:  initial  begin  $dumpfile("test.vcd");  $dumpvars(0,NTSC_frame_tb);  end  I assume that you would like to define some kind of default value with this assignment ?  wire [7:0] eav = 8'h0; wire [7:0] sav = 8'h0;  In Verilog this means that you will drive the wire to ground all the time. After removing this your simulation should run.  wire [7:0] eav; wire [7:0] sav;    Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi kaz,    maybe I wrong, but I would say your simulation is running forever. There is no condition for stopping the simulation like "$finish". I would add this :  //generate reset initial begin  reset = 1'b1;  reset =# 1000 1'b0;  #1000;  $finish; end  You can define the length of the simulation with the value above "$finish".  I don't know modelsim, but for other simulators you need to add something like this in case you want to use a waveform viever:  initial  begin  $dumpfile("test.vcd");  $dumpvars(0,NTSC_frame_tb);  end  I assume that you would like to define some kind of default value with this assignment ?  wire [7:0] eav = 8'h0; wire [7:0] sav = 8'h0;  In Verilog this means that you will drive the wire to ground all the time. After removing this your simulation should run.  wire [7:0] eav; wire [7:0] sav;    Kind regards  GPK  --- Quote End ---    Hi Kaz,  I found a typo in your source :  module NTSC_eav_sav  output [7:0] sav_data    Kind regards  GPK

[Altera_Forum]

Thanks pletz, 

 it works now. It was due to my initial values at declaration. I was vhdl minded apparently.   Many thanks for your time