ModelSim incorrectly simulates FPGA design

[Altera_Forum]

My AHDL program runs as expected on my FPGA, but when I simulate it in ModelSim, the result is wacky. 

Tools/Equipment: Windows 7 Quartus II 32-bit v12.0 sp2 Web Edition ModelSim SE-64 10.0c, using Gate Level Simulation, VHDL compiled library FPGA: Cyclone III EP3C16F484C8  Here's the essential AHDL code:  test_reg[].d = B"11"; test_reg[].clk = pld_clk; test_reg[].prn = !(!poreset/ & TEST_CONSTANT); test_reg[].clrn = !(!poreset/ & !TEST_CONSTANT);  pld_clk is running at 66.66 MHz, TEST_CONSTANT = B"10", and test_reg[] is a two bit DFF.  On the FPGA it runs as I expect:  -When poreset/ = VCC --> test_reg[] = B"11"  -When poreset/ = GND --> test_reg[] = B"10"  But in ModelSim:  -When poreset/ = VCC --> test_reg[] = B"U1"  -When poreset/ = GND --> test_reg[] = B"U0"  what is wrong with modelsim? I can't trust ModelSim for testing any more of my code.  Also, I get these messages in ModelSim after attempting to run the simulation, but then it seems to run fine (after it runs though a bunch of code). # ** Error: (vsim-3601) Iteration limit reached at time 0 ns.# steptrack::findloop2... # Starting tryFindLoop at time 0 ns and delta 99999 . # steptrack::findloop3... # Starting tryFindLoop at time 0 ns and delta 100001 . # Next activity is in 1 ns.# Next activity is in 14 ns.# Stopping as time has advanced to 1 ns !! # Could not find any active process to start the loop analysis.

[Altera_Forum]

reaching the iteration limit usually means you have a logic loop. There is nothing wrong with modelsim. The problem is with your design.

[Altera_Forum]

OK, thanks Tricky. Any tips on how to find a logic loop? Does ModelSim or Quartus come with any tools for this? Otherwise I have a lot of code to sift through.

[Altera_Forum]

you might get a warning from quartus, finding where it is may be difficult. If all the code was synchronous, you wouldnt get such a loop. But you only posted a small code snipppet. 

Of course having AHDL is going to make debugging a whole lot harder.  But if its working on FPGA, why the worry? (of course, again, being AHDL, its going to make changes a whole lot harder, as above.)