Modelsim Altera problems

[Altera_Forum]

Dear All, 

 I am recently using modelsim to debug my system because I heard it could easily show us the signals inside the system, not just the external signals. In addition, it won't synthesize signals away. Hence I must began to learn how to use it.  Now the problem is: I have made my input waveform inside Quartus II and exported it as a .vht file. Can this be used in the modelsim as testbench? Now when I add signals into waveforms, nothing appears on the black screen.  Thanks in advance!  regards

[Altera_Forum]

Yes, the exported .vht file can be used as testbench. Make sure you instantiate your design correctly. 

 After adding the signals to the waveform, you have to rerun the simulation. > restart -f > run -all  Alternatively you can log the signals and add to the waveform before you run the simulation. > log -r * > add wave * > run -all  *If I remember correctly..

[Altera_Forum]

yes, a vwf exported as a vht can be used in ModelSim as a testbench.

[Altera_Forum]

Hello, hycheah and thepancake, 

  Thanks for your help! Now the problem is that I don't know which files to put into my modelsim project. Here is the thing:    I first created an FIR and an FFT using MegaWizard Plug-In Manager. Then the following hdl files are created:  fir_comp_ast.vhd  fir_comp_st.v  tb_fir_comp.vhd  fir_com.vhd  my_fft_tb.v  my_fft_tb.vhd  my_fft_syn.v  my_fft.vhd    Then I connected the FIR and FFT in SOPC builder, between them I put a Dual Clock FIFO, then the following hdl files are created:    fir_comp_0.vhd  dc_fifo_0.v  my_fft_0.vhd  fir_fft_two_sopc.vhd (fir_fft_two_sopc is the name of my sopc system)  fir_fft_two_sopc_inst.vhd  fir_fft_two.vhd (instantiation of my SOPC system)    At this moment, I have tried myself. I have basically added every hdl files inside; I have even added some vho files (maybe they are not necessary).  However modelsim has given some compilation errors as follows:    fir_comp_ast.vhd failed with 1 errors:   ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_comp_ast.vhd(32): Library auk_dspip_lib not found. ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_comp_ast.vhd(33): (vcom-1136) Unknown identifier "auk_dspip_lib". ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_comp_ast.vhd(36): VHDL Compiler exiting      compile of fir_comp_ast.vhd failed with 1 errors.  ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): near "<byte 0x8b>": illegal character found in source ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): near "<byte 0x13>": illegal character found in source ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): near "<byte 0x9c>": illegal character found in source ** Error: D:/FYP_extra/fir_fft/fir_fft_two/fir_compiler-library/auk_dspip_lib_pkg_fir_90.vhd(1): VHDL Compiler exiting      # compile of my_fft.vhd failed with 1 errors. ** Error: D:/FYP_extra/fir_fft/fir_fft_two/my_fft.vhd(34): Library fft_lib not found. ** Error: D:/FYP_extra/fir_fft/fir_fft_two/my_fft.vhd(35): (vcom-1136) Unknown identifier "fft_lib". ** Error: D:/FYP_extra/fir_fft/fir_fft_two/my_fft.vhd(37): VHDL Compiler exiting    It seems that I have added some unnecessary files or missed some compulsory files? So, could you please advice on which files are necessary for my modelsim project?   Thank you so much for your patience!   Best regards

[Altera_Forum]

Hello, my friends, 

 Let me include more information about the situation.  After I compiled my test bench file fir_fft_two_tb.vht (exported from quartus ii), in the library it appears as three entity and one package (please see attachment), I really have no clue which one I should choose; hence I chose one by one to load the design.   when I loaded the first file fir_fft_two_vhd_check_tst, the result is shown in simulate_1.jpg  when I loaded the second file fir_fft_vhd_sample_tst, the result is shown in simulate_2.jpg  It didn't allow me to loaded the third file fir_fft_vhd_tb_types, hence I guess this one is not in use  Finally it says "error loading design" when I tried to load the last file fir_fft_vec_tst.  None of them worked, as you can see in my attachment, seems every signal is undefined! How could this be? Why is it totally different from the waveform I made inside quartus ii?  Please give some advice, I am going nuts here... Thank you so much!

[Altera_Forum]

looks like you're trying to simulate Altera's actual HDL files. when in the MegaWizard click step 2 and create simulation models in your language of choice. then compile them into your ModelSim project instead of the HDL files you've been trying. this is probably worth a read: 

 http://www.altera.com/literature/hb/qts/qts_qii53014.pdf

[Altera_Forum]

--- Quote Start ---  looks like you're trying to simulate Altera's actual HDL files. when in the MegaWizard click step 2 and create simulation models in your language of choice. then compile them into your ModelSim project instead of the HDL files you've been trying. this is probably worth a read:   http://www.altera.com/literature/hb/qts/qts_qii53014.pdf  --- Quote End ---    Exactly. I am simulating the HDL files generated by Quartus IP MegaWizard. Thanks for putting the link there.   While I am studying it, could you please tell me if I can draw my own testbench waveform using Modelsim Altera (the same way with the what Quartus II does, e.g. insert node, node finder and so forth)? I tried to search on Internet but couldn't find any useful information...  Thank you!

[Altera_Forum]

you can create a vwf in Quartus and export it as an HDL test bench to use in ModelSim. to view internal nodes you'll have navigate using the ModelSim GUI and/or save the commands into your simulation script so they show up every time you run it.

[Altera_Forum]

For Verilog - use the .vo files, not the .v files. The .vo files are functional simulation output files. I think VHDL should have equivalent .vho files.