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Hi there,
when i try to simulate my design, i receive the following msg: vsim -gui "+altera" -l msim_transcript -do "filename_run_msim_rtl_vhdl.do" # start time: 23:18:28 on mar 01,2015# ** error: (vsim-3170) could not find 'd:/####/simulation/modelsim/rtl_work.toplevelmoduletestbench'.# # error loading design# error: error loading design# pausing macro execution# macro ./filename_run_msim_rtl_vhdl.do paused at line 19 I`m not sure, where exactly the problem is. I also checked the .do file, but didn`t recognize smth special. So anybody knows about this failure and could help? Thanks a lot regardsLink Copied
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Hi Sek_tor, you may need to describe the simulation steps and also share your design here, so that i can try to duplicate the error.
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The error is saying that the specified design unit could not be found for loading. First, you may want to restart the simulator and re-execute the FILENAME_run_msim_rtl_vhdl.do to see it helps. You may also need to ensure the design unit has been compiled into correct library and that library is mapped correctly. That will help if you may attach the testcase here for debugging further.

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