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HI, I am using the Modelsim 6.5b for the timing analysis, but when I add the SDO file to the similation, an error occurs showing as follow:Loading instances from E:/FPGA/sin/simulation/modelsim/sin_v.sdo# ** Fatal: SDF files require Altera primitive library.
I am using Verilog HDL, and this error never occurs to my teammate who is using VHDL. THANKS FOR HELP!!!Link Copied
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it says that it requires altera's primitive library. try adding the library into the vsim when doing simulation:
vsim -L altera_ver work.<your top level test bench>
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