Modelsim Simualtion

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Modelsim Simualtion

1,104 Views

Hi ,

I have a very simple design in Quartus Web Pack ver 11.0 , and with it i have Modelsim-Altera Starter ver 6.6d. I dont see any output or response of the design when i run RTL simualtion .

I have used the same vhdl files and run the simulation in Modelsim ver 6.2 SE and i see results as expected ???

I have checked the mapping of lib using vmap it is ok .

What is the problem ???

Please find attached the screen shots and the project.

Thanks in advance

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.