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Modelsim error 3584 during RTL simulation

Altera_Forum
Honored Contributor II
1,207 Views

Hi, 

 

I'm attempting to perform an RTL simulation using Nativelink in Quartus Prime 15.1. My target device is an Intel EP4CE30F2917N (Cyclone IV) 

There's a parameterized I/O pad in my RTL which seems to cause ModelSim to post error 3584. See the transaction log below. I can't post the code, but given the info below, 

is there something I can do to resolve this error, or for the short term, suppress it from Nativelink. The .do file seems to be generated on each invocation which precludes inserting the -suppress argument there. Can it be inserted in some Quartus configuration file? 

 

vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" TestBench_2# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=""+acc"" TestBench_2 # Start time: 12:51:40 on Apr 06,2018# Loading work.TestBench_2# Loading work.MAIN# Loading work.IO_BUFFER# Loading work.CORE# Loading work.RESET_GEN# Loading work.CLOCK_GEN_PLL# Loading cycloneive_ver.cycloneive_pll# Loading cycloneive_ver.cycloneive_m_cntr# Loading cycloneive_ver.cycloneive_n_cntr# Loading cycloneive_ver.cycloneive_scale_cntr# Loading work.QUICK_USB# Loading work.WIDE_STROBE# Loading work.REGISTERS_BUILDINFO# Loading work.BUILD_INFO# Loading work.REGISTER# Loading work.REGISTERS_SCRATCH# Loading work.REGISTERS_SCRIPTCONTROL# Loading work.REGISTERS_SUPPLYCONTROL# Loading work.REGISTERS_DUTCONTROL# Loading work.REGISTERS_PMICCONTROL# Loading work.REGISTERS_RFFEINTERFACE# Loading work.REGISTER_FIFO_WRITE# Loading altera_mf_ver.dcfifo# Loading altera_mf_ver.dcfifo_mixed_widths# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES# Loading altera_mf_ver.dcfifo_low_latency# Loading altera_mf_ver.ALTERA_MF_HINT_EVALUATION# Loading altera_mf_ver.dcfifo_dffpipe# Loading work.REGISTER_FIFO_READ# Loading work.REGISTERS_I2CCONTROL# Loading work.REGISTERS_SPMIINTERFACE# Loading work.REGISTERS_MDMCONTROL# Loading work.REGISTERS_PHS_CONTROL# Loading work.REGISTERS_MISC_CONTROL# Loading work.SCRIPT_ENGINE# Loading work.I2C_MASTER_2# Loading work.RFFE_WRAPPER# Loading work.CLOCK_SWITCH# Loading work.CLOCK_CROSS_STROBE# Loading work.CLOCK_CROSS_STROBE_2# Loading work.RFFE_MASTER_2# Loading work.RFFE_MUX# Loading work.GRFC_MUX# Loading cycloneive_ver.cycloneive_io_obuf# Loading cycloneive_ver.cycloneive_io_ibuf# Loading altera_mf_ver.dcfifo_async# Loading altera_mf_ver.dcfifo_fefifo# ** Error (suppressible): (vsim-3584) C:/Users/c_srodge/Desktop/Phaser/ControlBoard/FPGA/PH422/Source/IO/IO_Buffer.v(27): Module parameter 'differential_mode' not found for override.# Time: 0 ps Iteration: 0 Instance: /TestBench_2/Main_TB/IO_Buffer_FX2Data/GENERATE_IO_BUFFER[0]/OutBuffer File: /build/swbuild/SJ/nightly/16.1/196/l64/work/modelsim/eda/sim_lib/cycloneive_atoms.v# ** Error (suppressible): (vsim-3584) C:/Users/c_srodge/Desktop/Phaser/ControlBoard/FPGA/PH422/Source/IO/IO_Buffer.v(27): Module parameter 'differential_mode' not found for override.# Time: 0 ps Iteration: 0 Instance: /TestBench_2/Main_TB/IO_Buffer_FX2Data/GENERATE_IO_BUFFER[1]/OutBuffer File: /build/swbuild/SJ/nightly/16.1/196/l64/work/modelsim/eda/sim_lib/cycloneive_atoms.v# ** Error (suppressible): (vsim-3584) C:/Users/c_srodge/Desktop/Phaser/ControlBoard/FPGA/PH422/Source/IO/IO_Buffer.v(27): Module parameter 'differential_mode' not found for override.# Time: 0 ps Iteration: 0 Instance: /TestBench_2/Main_TB/IO_Buffer_FX2Data/GENERATE_IO_BUFFER[2]/OutBuffer File: /build/swbuild/SJ/nightly/16.1/196/l64/work/modelsim/eda/sim_lib/cycloneive_atoms.v# ** Error (suppressible): (vsim-3584) C:/Users/c_srodge/Desktop/Phaser/ControlBoard/FPGA/PH422/Source/IO/IO_Buffer.v(27): Module parameter 'differential_mode' not found for override.# Time: 0 ps Iteration: 0 Instance: /TestBench_2/Main_TB/IO_Buffer_FX2Data/GENERATE_IO_BUFFER[3]/OutBuffer File: /build/swbuild/SJ/nightly/16.1/196/l64/work/modelsim/eda/sim_lib/cycloneive_atoms.v# ** Error (suppressible): (vsim-3584) C:/Users/c_srodge/Desktop/Phaser/ControlBoard/FPGA/PH422/Source/IO/IO_Buffer.v(27): Module parameter 'differential_mode' not found for override.# Time: 0 ps Iteration: 0 Instance: /TestBench_2/Main_TB/IO_Buffer_FX2Data/GENERATE_IO_BUFFER[4]/OutBuffer File: /build/swbuild/SJ/nightly/16.1/196/l64/work/modelsim/eda/sim_lib/cycloneive_atoms.v# ** Error (suppressible): (vsim-3584) C:/Users/c_srodge/Desktop/Phaser/ControlBoard/FPGA/PH422/Source/IO/IO_Buffer.v(27): Module parameter 'differential_mode' not found for override.
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
349 Views

Hi, 

 

Try by loading the design in ModelSim manually instead of native-like for simulation OR 

Try simulating by removing the IO buffer module with native-like. 

The error may be because of how IO buffers are handled in the design. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
AMath1
Beginner
349 Views

I am also facing same error on parameterised iobuffer . Did anyone solve this issue.. any leads is appreciated...

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