Modelsim simulation using Arria 10 device

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Hello, 

  1) I generated .vo for an UP DOWN counter (device is 10AS016E4F29I3SG) using Quartus Prime 16.0 standard edition (30 days trial version) and did gate level simulation using Modelsim Altera which came along with Quartus 13.1. Request help to resolve the following error.   vsim -L twentynm -do up_down_counter_run_msim_gate_verilog.do -l msim_transcript -gui gate_work.up_down_counterstimul # Loading gate_work.up_down_counterstimul# Loading gate_work.up_down_counter# ** Error: (vsim-3033) up_down_counter.vo(229): Instantiation of 'dffeas' failed. The design unit was not found.# # Region: /up_down_counterstimul/up_down_counter# Searched libraries:# C:/altera/13.1/modelsim_ase/altera/vhdl/twentynm# D:/Process/Essence/FPGA_training/quartus_16.0_projects/up_down_counter/simulation/modelsim/gate_work# ** Error: (vsim-3033) up_down_counter.vo(285): Instantiation of 'dffeas' failed. The design unit was not found.# Error loading design   2) Generated Arria10 Transceiver native PHY IP (device is 10AS016E4F29I3SG) using Quartus Prime 16.0 standard edition (30 days trial version) and did RTL simulation using Modelsim Altera which came along with Quartus 13.1. Request help to resolve the following error.  # vsim -L arria10_altera_xcvr_native_a10_160 -do arria10_run_msim_rtl_verilog.do -l msim_transcript -gui work.arria10 # Loading work.arria10# Loading sv_std.std# Loading altera_common_sv_packages.altera_xcvr_native_a10_functions_h# Loading arria10_altera_xcvr_native_a10_160.arria10_altera_xcvr_native_a10_160_outs3xi# Loading arria10_altera_xcvr_native_a10_160.alt_xcvr_native_rcfg_opt_logic_outs3xi# ** Fatal: Error occurred in protected context.# Time: 0 ps Iteration: 0 Protected: /arria10/xcvr_native_a10_0/g_xcvr_native_insts[0]/twentynm_xcvr_native_inst/<protected>/<protected>/<protected>/<protected> File: nofile# FATAL ERROR while loading design# Error loading design